gcc/ChangeLog:
PR translation/80280
* config/i386/msformat-c.c (ms_printf_flag_specs): Initialize new
data member added in r247778.
(ms_scanf_flag_specs, ms_strftime_flag_specs): Same.
From-SVN: r247801
When a processor enters a fast interrupts handler, and duplicate
register banks are configured, the processor saves the user context by
saving the registers in the main register bank to these additional
registers in the duplicate register bank. In this fast interrupt
context, when you specify the rgf_banked_regs option,the compiler does
not save the registers duplicated in the additional register bank are
not saved.
gcc/
2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
Andrew Burgess <andrew.burgess@embecosm.com>
* config/arc/arc.c (ARC_AUTOBLINK_IRQ_P): Consider fast interrupts
case also.
(ARC_AUTOFP_IRQ_P): Likewise.
(ARC_AUTO_IRQ_P): Likewise.
(rgf_banked_register_count): New variable.
(parse_mrgf_banked_regs_option): New function.
(arc_override_options): Handle rgf_banked_regs option.
(arc_handle_interrupt_attribute): Add firq option.
(arc_compute_function_type): Return fast irq type when required.
(arc_must_save_register): Handle fast interrupts.
(arc_expand_prologue): Do not emit dwarf info for fast interrupts.
(arc_return_address_regs): Update.
* config/arc/arc.h (arc_return_address_regs): Update.
(arc_function_type): Add fast interrupt type.
(ARC_INTERRUPT_P): Update.
(RC_FAST_INTERRUPT_P): Define.
* config/arc/arc.md (simple_return): Update for fast interrupts.
(p_return_i): Likewise.
* config/arc/arc.opt (mrgf-banked-regs): New option.
* doc/invoke.texi (mrgf-banked-regs): Document.
testsuite/
2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
Andrew Burgess <andrew.burgess@embecosm.com>
* gcc.target/arc/firq-1.c: New file.
* gcc.target/arc/firq-2.c: Likewise.
* gcc.target/arc/firq-3.c: Likewise.
* gcc.target/arc/firq-4.c: Likewise.
* gcc.target/arc/firq-5.c: Likewise.
* gcc.target/arc/firq-6.c: Likewise.
Co-Authored-By: Andrew Burgess <andrew.burgess@embecosm.com>
From-SVN: r247796
The AUX_IRQ_CTRL register controls the behavior of automated register
save and restore or prologue and epilogue sequences during a non-fast
interrupt entry and exit, and context save and restore instructions.
A user passes to the compiler the configuration of the AUX_IRQ_CTRL
register via mirq-ctrl-saved option. This option, specifies
gneral-purposes registers that the processor saves/restores on
interrupt entry and exit, and it is only valid for ARC EM and ARC HS
cores.
gcc/
2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (irq_ctrl_saved): New variable.
(ARC_AUTOBLINK_IRQ_P): Define.
(ARC_AUTOFP_IRQ_P): Likewise.
(ARC_AUTO_IRQ_P): Likewise.
(irq_range): New function.
(arc_must_save_register): Likewise.
(arc_must_save_return_addr): Likewise.
(arc_dwarf_emit_irq_save_regs): Likewise.
(arc_override_options): Handle deferred options.
(MUST_SAVE_REGISTER): Deleted, replaced by arc_must_save_register.
(MUST_SAVE_RETURN_ADDR): Deleted, replaced by
arc_must_save_return_addr.
(arc_compute_frame_size): Handle automated save and restore of
registers.
(arc_expand_prologue): Likewise.
(arc_expand_epilogue): Likewise.
* config/arc/arc.md (stack_irq_dwarf): New unspec instruction.
* config/arc/arc.opt (mirq-ctrl-saved): New option.
* doc/invoke.texi (mirq-ctrl-saved): Document option.
testsuite/
2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/interrupt-5.c: Newfile.
* gcc.target/arc/interrupt-6.c: Likewise.
* gcc.target/arc/interrupt-7.c: Likewise.
* gcc.target/arc/interrupt-8.c: Likewise.
* gcc.target/arc/interrupt-9.c: Likewise.
From-SVN: r247795
The test reports bogus failures because the loop variable i is declared
as int, and the constant expected in the dump doesn't fit in an int for avr.
Fixed by explicitly using __INT32_TYPE__ for targets with __SIZEOF_INT__ < 4.
gcc/testsuite/
2017-05-09 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
* gcc.dg/tree-ssa/cunroll-13.c: Use __INT32_TYPE__ for
for targets with __SIZEOF_INT__ < 4.
From-SVN: r247782
2017-05-09 Richard Biener <rguenther@suse.de>
* tree-vrp.c (get_single_symbol): Add assert that we don't
get overflowed constants as invariant part.
(compare_values_warnv): Add comment before the TREE_NO_WARNING
checks. Use wi::cmp instead of recursing for integer constants.
(compare_values): Just ignore whether we assumed undefined
overflow instead of failing the compare.
(extract_range_for_var_from_comparison_expr): Add comment before the
TREE_NO_WARNING sets.
(test_for_singularity): Likewise.
(extract_range_from_comparison): Do not disable optimization
when we assumed undefined overflow.
(extract_range_basic): Remove init of unused var.
From-SVN: r247781
2017-05-09 Richard Biener <rguenther@suse.de>
* tree-vrp.c (vrp_int_const_binop): Use wide-ints and simplify.
(extract_range_from_multiplicative_op_1): Adjust.
(extract_range_from_binary_expr_1): Use int_const_binop.
From-SVN: r247779
gcc/testsuite/ChangeLog:
2017-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/80101
* gcc.target/powerpc/pr80101-1.c: New test.
gcc/ChangeLog:
2017-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/80101
* config/rs6000/power6.md: Replace store_data_bypass_p calls with
rs6000_store_data_bypass_p in seven define_bypass directives and
in several comments.
* config/rs6000/rs6000-protos.h: Add prototype for
rs6000_store_data_bypass_p function.
* config/rs6000/rs6000.c (rs6000_store_data_bypass_p): New
function implements slightly different (rs6000-specific) semantics
than store_data_bypass_p, returning false rather than aborting
with assertion error when arguments do not satisfy the
requirements of store data bypass.
(rs6000_adjust_cost): Replace six calls of store_data_bypass_p with
rs6000_store_data_bypass_p.
From-SVN: r247777
gcc/
2017-05-08 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa-protos.h
(xtensa_initial_elimination_offset): New declaration.
* config/xtensa/xtensa.c (xtensa_initial_elimination_offset):
New function. Move its body from the INITIAL_ELIMINATION_OFFSET
macro definition, add case for FRAME_POINTER_REGNUM when
FRAME_GROWS_DOWNWARD.
* config/xtensa/xtensa.h (FRAME_GROWS_DOWNWARD): New macro
definition.
(INITIAL_ELIMINATION_OFFSET): Replace body with call to
xtensa_initial_elimination_offset.
From-SVN: r247771
* decl.c (builtin_function_1): Set DCL_ANTICIPATED before pushing.
(start_preparsed_function): Do decl pushing before setting
current_funciton_decl and announcing it.
From-SVN: r247754
* include/std/optional: Use a separate static_assert per condition.
* testsuite/20_util/optional/cons/value_neg.cc: Update dg-error line
numbers.
From-SVN: r247748
The movsi and movdi constraints allowed the source to be any
absolute symbolic expression ("S"). That's OK for operands that
have already been vetted by the aarch64_mov_operand predicate but
causes problems if the register allocator substitutes an equivalence
(the usual "the constraints can't accept more than the predicates"
restriction).
Although all other uses of "S" in the backend are redundant and could
in principle be removed, "S" itself is a publicly-documented constraint
and so we'd have to keep its definition. This patch therefore adds a
new "Usa" constraint for legitimate absolute address operands.
2017-05-08 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/constraints.md (Usa): New constraint.
* config/aarch64/aarch64.md (*movsi_aarch64, *movdi_aarch64): Use it.
From-SVN: r247746
TM_MULTILIB_CONFIG is not set in config.gcc when building with multilib
for arm targets, leading to config/arm/t-multilib not including any of
the files (t-aprofile and t-rmprofile) definining the architecture and
FPU to build multilib for. This patch fixes that by setting
TM_MULTILIB_CONFIG to with_multilib_list's value after it has been
checked. It also fix a trailing whitespace issue.
2017-05-08 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config.gcc (arm*-*-*): Set TM_MULTILIB_CONFIG from
with_multilib_list after it has been checked.
From-SVN: r247741
2017-05-08 Richard Biener <rguenther@suse.de>
* tree-vrp.c (gimple_assign_nonzero_warnv_p): Rename to ...
(gimple_assign_nonzero): ... this and remove strict_overflow_p
argument.
(gimple_stmt_nonzero_warnv_p): Rename to ...
(gimple_stmt_nonzero_p): ... this and remove strict_overflow_p
argument.
(vrp_stmt_computes_nonzero): Remove strict_overflow_p argument.
(extract_range_basic): Adjust, do not disable propagation on
strict overflow sensitive simplification.
(vrp_visit_cond_stmt): Likewise.
From-SVN: r247738
This fixes a few failures on ARM and AArch64 due to a recent change in
alignment peeling by switching the vector cost model off.
Tested on AArch64, ARM and x64 - committed as obvious.
testsuite/
* gcc.dg/vect/vect-44.c: Add -fno-vect-cost-model.
* gcc.dg/vect/vect-50.c: Likewise.
From-SVN: r247737
2017-05-07 Jeff Law <law@redhat.com>
Revert:
2017-05-06 Jeff Law <law@redhat.com>
PR tree-optimization/78496
* tree-vrp.c (simplify_assert_expr_using_ranges): Remove debugging
code.
PR tree-optimization/78496
* tree-vrp.c (simplify_assert_expr_using_ranges): New function.
(simplify_stmt_using_ranges): Call it.
(vrp_dom_walker::before_dom_children): Extract equivalences
from an ASSERT_EXPR with an equality comparison against a
constant.
Revert:
2017-05-06 Jeff Law <law@redhat.com>
PR tree-optimization/78496
* gcc.dg/tree-ssa/ssa-thread-16.c: New test.
* gcc.dg/tree-ssa/ssa-thread-17.c: New test.
From-SVN: r247727
PR tree-optimization/78496
* tree-vrp.c (simplify_assert_expr_using_ranges): New function.
(simplify_stmt_using_ranges): Call it.
(vrp_dom_walker::before_dom_children): Extract equivalences
from an ASSERT_EXPR with an equality comparison against a
constant.
PR tree-optimization/78496
* gcc.dg/tree-ssa/ssa-thread-16.c: New test.
* gcc.dg/tree-ssa/ssa-thread-17.c: New test.
From-SVN: r247721
If we decide to allocate a call-clobbered register R to a value that
is live across a call, LRA will create a new spill register TMPR,
insert:
TMPR <- R
before the call and
R <- TMPR
after it. But if we then failed to allocate a register to TMPR, we would
always spill it to the stack, even if R was known to be equivalent to
a constant or to some existing memory location. And on AArch64, we'd
always fail to allocate such a register for 128-bit Advanced SIMD modes,
since no registers of those modes are call-preserved.
This patch avoids the problem by copying the equivalence information
from the original pseudo to the spill register. It means that the
code for the testcase is as good with -O2 as it is with -O,
whereas previously the -O code was better.
[Based on the code ARM contributed in branches/ARM/sve-branch@247248]
2017-05-06 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* lra-constraints.c (lra_copy_reg_equiv): New function.
(split_reg): Use it to copy equivalence information from the
original register to the spill register.
gcc/testsuite/
* gcc.target/aarch64/spill_1.c: New test.
From-SVN: r247720
RTL has no distinction between signed and unsigned values, so it
doesn't make sense to test for signed overflow.
2017-05-06 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
PR rtl-optimization/75964
* simplify-rtx.c (simplify_const_relational_operation): Remove
invalid handling of comparisons of integer ABS.
gcc/testsuite/
PR rtl-optimization/75964
* gcc.dg/torture/pr75964.c: New test.
From-SVN: r247719
