Commit graph

4735 commits

Author SHA1 Message Date
Mike Frysinger
d9e217e950 sim: cgen: move cgen-types.h include to cgen-defs.h
The cgen-types.h header sets up types that are needed by cgen-defs.h,
so move the include out of sim-main.h and to that header.  It might
be needed in other specific modules, but for now let's kick it out of
sim-main.h to make some progress.  Things still build with just this.
2022-12-23 00:51:14 -05:00
Mike Frysinger
a4c4d804d6 Revert "sim: mn10300: drop unused sim-main.c"
This reverts commit 681a422b85.

I missed that this was included via common/sim-inline.c.  I thought
I had grepped the top of the tree, but I must have only done mn10300.

Add a comment to make it clear where/how this file is used.
2022-12-23 00:22:53 -05:00
Mike Frysinger
681a422b85 sim: mn10300: drop unused sim-main.c
Nothing compiles or references this, so punt it.
2022-12-22 23:39:35 -05:00
Mike Frysinger
b15fa15bc4 sim: endian: move bfd.h from header to source
The bfd APIs are used only by sim-n-endian.h which is only included by
sim-endian.c, so move the bfd.h include there and out of sim-endian.h
which is included by many other modules.
2022-12-22 22:06:52 -05:00
Mike Frysinger
6cf3ddd23e sim: move bfd.h include out of sim-main.h
Not all arches include this in sim-main.h, and the ones that do don't
actually use bfd defines in the sim-main.h header.  Prune it to make
sim-main.h simpler so we can kill it off entirely in the future.

We add the include to the files that utilize e.g. bfd_vma though.
2022-12-22 22:06:12 -05:00
Mike Frysinger
4c337f2dd3 sim: mcore: replace custom "word" type with int32_t
This is a 32-bit architecture with 32-bit registers, so replace the
custom "word" long int typedef with an explicit int32_t.  This is
a correctness fix since long will be 64-bits on most 64-bit hosts.
2022-12-22 21:55:47 -05:00
Mike Frysinger
be2e4e6538 sim: moxie: replace custom "word" type with int32_t
This is a 32-bit architecture with 32-bit registers, so replace the
custom "word" int typedef with an explicit int32_t.  Practically
speaking, this produces the same code, but it should hopefully make
it easier to merge common code in the future.
2022-12-22 21:55:47 -05:00
Mike Frysinger
547eedc132 sim: cr16/d10v/mcore/moxie: clean up unused word & uword types
Nothing actually uses these, so punt them.  Some of the ports are
using local "word" types, but we'll clean those up in a follow up.
2022-12-22 21:55:47 -05:00
Mike Frysinger
3841a73a27 sim: mips: trim redundant igen settings
These variables are setting the same value as the defaults.  Trim
this redundant logic to make it easier to see the real differences
so we can try to keep unifying cases.
2022-12-22 21:29:21 -05:00
Mike Frysinger
022e1fb26c sim: mips: merge mips64* with existing multi-run build
Change the default (unhandled) mips64* targets to use the existing
mips64 multi-run build.  It already handles the formats, we just
have to list the mips8000 bfd for it.
2022-12-22 21:24:09 -05:00
Mike Frysinger
a54eee6db6 sim: mips: merge mips64vr5000 with existing multi-run build
The existing mips64vr-* multi-run build already handles mips5000
targets, so reuse that for mips64vr5* targets too.  This moves
more logic from build-time to runtime so we can have a single
binary that supports many targets.
2022-12-22 21:20:44 -05:00
Mike Frysinger
697e27f0ee sim: mips: switch from SIM_ADDR to address_word
The latter type matches the address size configured for this sim.

Also take the opportunity to simplify printf logic by leveraging
PRI* macros.
2022-12-22 20:10:13 -05:00
Mike Frysinger
ae0faac067 sim: v850: switch from SIM_ADDR to address_word
The latter type matches the address size configured for this sim.
2022-12-22 19:46:36 -05:00
Mike Frysinger
63fd5b5dda sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]
We've been using SIM_ADDR which has always been 32-bit.  This means
the upper 32-bit address range in 64-bit sims is inaccessible.  Use
64-bit addresses all the time since we want the APIs to be stable
regardless of the active arch backend (which can be 32 or 64-bit).

The length is also 64-bit because it's completely feasible to have
a program that is larger than 4 GiB in size/image/runtime.  Forcing
the caller to manually chunk those accesses up into 4 GiB at a time
doesn't seem useful to anyone.

Bug: https://sourceware.org/PR7504
2022-12-22 19:29:24 -05:00
Mike Frysinger
20fea6638f sim: use bfd_vma when reading start addr from bfd info
Since SIM_ADDR is always 32-bit, it might truncate the address with
64-bit ELFs.  Since we load that addr from the bfd, use the bfd_vma
type which matches the bfd_get_start_address API.
2022-12-22 19:29:10 -05:00
Mike Frysinger
7dc3ab9125 sim: m32r: include sim-hw.h for sim_hw_parse 2022-12-22 19:13:40 -05:00
Mike Frysinger
2ac6aa431e sim: mips: merge mips64vr4300 with existing multi-run build
The existing mips64vr-* multi-run build already handles mips4300
targets, so reuse that for mips64vr43* targets too.  This moves
more logic from build-time to runtime so we can have a single
binary that supports many targets.
2022-12-22 19:04:23 -05:00
Mike Frysinger
2011a54779 sim: mips: match target on cpu settings
We don't need to enforce larger target settings when the only thing
the sim should care about is the CPU target.  So reduce most of the
target matches to only check the CPU.
2022-12-21 22:27:12 -05:00
Mike Frysinger
d455df988a sim: mips: move fpu bitsize defines to top-level configure
This drops support for the --enable-sim-float configure option,
but it's not clear anyone ever actually used that.  Eventually
we'll want this to be a runtime option anyways.
2022-12-21 22:27:12 -05:00
Mike Frysinger
19b11256a5 sim: mips: move bitsize defines to top-level configure
Since the msb value is always defined as the wordsize-1, stop
hardcoding that value directly, and use a CPP value instead.
2022-12-21 22:27:12 -05:00
Mike Frysinger
2d5700ad4e sim: mips: move subtarget defines to top-level configure
We want to kill off mips/configure entirely.  Move this small part
out now to get started.
2022-12-21 22:27:11 -05:00
Mike Frysinger
0fb6c560ff sim: mips: always resolve active bfd mach dynamically
Don't assume that the default bfd that we configured for is the one
that is always active when running a program.  We already have access
to the real runtime value, so use it directly.  This simplifies the
code quite a bit, and will make it easier to support multiple mach's
in a single binary.
2022-12-21 22:27:11 -05:00
Mike Frysinger
f4ac230605 sim: hw-config.h: move generation to top-level
In order to compile arch objects from the top-level, we need to
generate the hw-config.h header, so move that logic up to the top
level first.
2022-12-21 22:21:25 -05:00
Mike Frysinger
3d04211786 sim: build: hoist lists of hw devices up
We need these in the top-level to generate libsim.a, but also in the
subdirs to generate hw-config.h.  Move it to the local.mk, and pass
it down when running recursive make.  This avoids duplication, and
makes it available to both.  We can simplify this once we move the
various steps up to the top-level too.
2022-12-21 22:21:25 -05:00
Mike Frysinger
d47ea1b9c1 sim: build: hoist lists of common objects up
In order to create libsim.a in the common dir, we need the list of
objects for each target.  To avoid duplicating the list with the
recursive make in each port, pass it down as a variable.  This is
a temporary hack until the top-level creates libsim.a for ports.
2022-12-21 22:21:25 -05:00
Mike Frysinger
8df77a27a3 sim: fully merge sim_cpu_base into sim_cpu
Now that all ports have migrated to the new framework, drop support
for the old sim_cpu_base layout.  There's a lot of noise here, so
it's been split into a dedicated commit.
2022-12-21 00:00:19 -05:00
Mike Frysinger
4a21ad1e76 sim: enable common sim_cpu usage everywhere
All ports should be migrated now.  Drop the SIM_HAVE_COMMON_SIM_CPU
knob and require it be used everywhere now.
2022-12-21 00:00:18 -05:00
Mike Frysinger
4c3c31719b sim: or1k: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
9a9db21d12 sim: m32r: invert sim_cpu storage
The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
63c5692305 sim: lm32: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
06f4b7b6d1 sim: iq2000: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
811727abbd sim: frv: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
8681713743 sim: cris: invert sim_cpu storage
The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
ef7878a286 sim: bpf: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
53891d9a7c sim: cgen: prep for inverting sim_cpu storage
Some common cgen code changes to allow cgen ports to invert their
sim_cpu storage one-by-one.
2022-12-21 00:00:01 -05:00
Mike Frysinger
5409cab77e sim: riscv: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
3d165c11f0 sim: pru: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
86ecb89bb7 sim: example-synacor: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
3fbdc6f908 sim: h8300: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
79d784aef9 sim: m68hc11: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
8e9408080b sim: mips: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
6d53d06992 sim: v850: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
620dd532fe sim: mcore: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6a08ae198b sim: aarch64: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
9dfc46c3d9 sim: microblaze: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
f246dc7285 sim: avr: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
778ef9bcbb sim: moxie: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
1c867d708c sim: msp430: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6780d3731e sim: ft32: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6adb107113 sim: bfin: invert sim_cpu storage 2022-12-21 00:00:00 -05:00