sim: pru: invert sim_cpu storage
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86ecb89bb7
commit
3d165c11f0
3 changed files with 31 additions and 8 deletions
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@ -130,6 +130,8 @@ write_regval (uint32_t val, uint32_t *reg, uint32_t regsel)
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static uint32_t
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imem_wordaddr_to_byteaddr (SIM_CPU *cpu, uint16_t wa)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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return (((uint32_t) wa << 2) & IMEM_ADDR_MASK) | PC_ADDR_SPACE_MARKER;
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}
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@ -147,6 +149,7 @@ static inline void
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pru_reg2dmem (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
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int regn, int regb)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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/* GDB assumes unconditional access to all memories, so enable additional
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checks only in standalone mode. */
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bool standalone = (STATE_OPEN_KIND (CPU_STATE (cpu)) == SIM_OPEN_STANDALONE);
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@ -196,6 +199,7 @@ static inline void
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pru_dmem2reg (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
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int regn, int regb)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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/* GDB assumes unconditional access to all memories, so enable additional
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checks only in standalone mode. */
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bool standalone = (STATE_OPEN_KIND (CPU_STATE (cpu)) == SIM_OPEN_STANDALONE);
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@ -247,6 +251,7 @@ pru_dmem2reg (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
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static void
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set_initial_gprs (SIM_CPU *cpu)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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int i;
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/* Set up machine just out of reset. */
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@ -325,6 +330,8 @@ static void
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pru_sim_xin_mac (SIM_DESC sd, SIM_CPU *cpu, unsigned int rd_regn,
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unsigned int rdb, unsigned int length)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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if (rd_regn < 25 || (rd_regn * 4 + rdb + length) > (27 + 1) * 4)
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sim_io_error (sd, "XIN MAC: invalid transfer regn=%u.%u, length=%u\n",
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rd_regn, rdb, length);
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@ -348,6 +355,8 @@ static void
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pru_sim_xin (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
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unsigned int rd_regn, unsigned int rdb, unsigned int length)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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if (wba == 0)
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{
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pru_sim_xin_mac (sd, cpu, rd_regn, rdb, length);
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@ -393,6 +402,7 @@ static void
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pru_sim_xout_mac (SIM_DESC sd, SIM_CPU *cpu, unsigned int rd_regn,
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unsigned int rdb, unsigned int length)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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const int modereg_accessed = (rd_regn == 25);
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/* Multiple Accumulate. */
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@ -453,6 +463,8 @@ static void
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pru_sim_xout (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
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unsigned int rd_regn, unsigned int rdb, unsigned int length)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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if (wba == 0)
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{
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pru_sim_xout_mac (sd, cpu, rd_regn, rdb, length);
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@ -482,6 +494,8 @@ static void
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pru_sim_xchg (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
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unsigned int rd_regn, unsigned int rdb, unsigned int length)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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if (wba == XFRID_SCRATCH_BANK_0 || wba == XFRID_SCRATCH_BANK_1
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|| wba == XFRID_SCRATCH_BANK_2 || wba == XFRID_SCRATCH_BANK_PEER)
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{
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@ -508,6 +522,7 @@ pru_sim_xchg (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
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static void
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pru_sim_syscall (SIM_DESC sd, SIM_CPU *cpu)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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/* If someday TI confirms that the "reserved" HALT opcode fields
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can be used for extra arguments, then maybe we can embed
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the syscall number there. Until then, let's use R1. */
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@ -525,6 +540,7 @@ static void
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sim_step_once (SIM_DESC sd)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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const struct pru_opcode *op;
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uint32_t inst;
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uint32_t _RDVAL, OP2; /* intermediate values. */
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@ -635,16 +651,20 @@ sim_engine_run (SIM_DESC sd,
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static sim_cia
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pru_pc_get (sim_cpu *cpu)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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/* Present PC as byte address. */
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return imem_wordaddr_to_byteaddr (cpu, cpu->pru_cpu.pc);
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return imem_wordaddr_to_byteaddr (cpu, pru_cpu->pc);
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}
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/* Implement callback for standard CPU_PC_STORE routine. */
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static void
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pru_pc_set (sim_cpu *cpu, sim_cia pc)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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/* PC given as byte address. */
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cpu->pru_cpu.pc = imem_byteaddr_to_wordaddr (cpu, pc);
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pru_cpu->pc = imem_byteaddr_to_wordaddr (cpu, pc);
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}
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@ -652,6 +672,8 @@ pru_pc_set (sim_cpu *cpu, sim_cia pc)
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static int
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pru_store_register (SIM_CPU *cpu, int rn, const void *memory, int length)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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if (rn < NUM_REGS && rn >= 0)
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{
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if (length == 4)
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@ -675,6 +697,7 @@ pru_store_register (SIM_CPU *cpu, int rn, const void *memory, int length)
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static int
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pru_fetch_register (SIM_CPU *cpu, int rn, void *memory, int length)
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{
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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long ival;
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if (rn < NUM_REGS && rn >= 0)
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@ -751,7 +774,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
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current_target_byte_order = BFD_ENDIAN_LITTLE;
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
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if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct pru_regset)) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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@ -831,6 +854,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd,
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char * const *argv, char * const *env)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
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host_callback *cb = STATE_CALLBACK (sd);
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SIM_ADDR addr;
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@ -41,7 +41,7 @@
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#define XFRID_SCRATCH_BANK_PEER 14
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#define XFRID_MAX 255
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#define CPU (cpu->pru_cpu)
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#define CPU (*pru_cpu)
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#define PC (CPU.pc)
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#define PC_byteaddr ((PC << 2) | PC_ADDR_SPACE_MARKER)
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@ -19,6 +19,8 @@
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#ifndef PRU_SIM_MAIN
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#define PRU_SIM_MAIN
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#define SIM_HAVE_COMMON_SIM_CPU
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#include <stdint.h>
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#include <stddef.h>
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#include "pru.h"
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@ -78,9 +80,6 @@ struct pru_regset
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int insts;
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};
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struct _sim_cpu {
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struct pru_regset pru_cpu;
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sim_cpu_base base;
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};
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#define PRU_SIM_CPU(cpu) ((struct pru_regset *) CPU_ARCH_DATA (cpu))
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#endif /* PRU_SIM_MAIN */
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