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sim: mips: invert sim_cpu storage

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This commit is contained in:
Mike Frysinger 2016-08-13 01:30:58 -07:00
parent 6d53d06992
commit 8e9408080b
2 changed files with 90 additions and 73 deletions
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112
sim/mips/interp.c
View file

@ -351,7 +351,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
/* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct mips_sim_cpu))
!= SIM_RC_OK)
return 0;
cpu = STATE_CPU (sd, 0); /* FIXME */
@ -666,19 +667,21 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
int rn;
for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
{
struct mips_sim_cpu *mips_cpu = MIPS_SIM_CPU (cpu);
if (rn < 32)
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
mips_cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
mips_cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
else if ((rn >= 33) && (rn <= 37))
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
mips_cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
else if ((rn == SRIDX)
|| (rn == FCR0IDX)
|| (rn == FCR31IDX)
|| ((rn >= 72) && (rn <= 89)))
cpu->register_widths[rn] = 32;
mips_cpu->register_widths[rn] = 32;
else
cpu->register_widths[rn] = 0;
mips_cpu->register_widths[rn] = 0;
}
@ -855,7 +858,9 @@ mips_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
numbering one. We need to know what the width of each logical
register number is for the architecture being simulated. */
if (cpu->register_widths[rn] == 0)
struct mips_sim_cpu *mips_cpu = MIPS_SIM_CPU (cpu);
if (mips_cpu->register_widths[rn] == 0)
{
sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register store ignored)\n", rn);
return 0;
@ -863,18 +868,18 @@ mips_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
{
cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
if (cpu->register_widths[rn] == 32)
mips_cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
if (mips_cpu->register_widths[rn] == 32)
{
if (length == 8)
{
cpu->fgr[rn - FGR_BASE] =
mips_cpu->fgr[rn - FGR_BASE] =
(uint32_t) T2H_8 (*(uint64_t*)memory);
return 8;
}
else
{
cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory);
mips_cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory);
return 4;
}
}
@ -882,28 +887,28 @@ mips_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
{
if (length == 8)
{
cpu->fgr[rn - FGR_BASE] = T2H_8 (*(uint64_t*)memory);
mips_cpu->fgr[rn - FGR_BASE] = T2H_8 (*(uint64_t*)memory);
return 8;
}
else
{
cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory);
mips_cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory);
return 4;
}
}
}
if (cpu->register_widths[rn] == 32)
if (mips_cpu->register_widths[rn] == 32)
{
if (length == 8)
{
cpu->registers[rn] =
mips_cpu->registers[rn] =
(uint32_t) T2H_8 (*(uint64_t*)memory);
return 8;
}
else
{
cpu->registers[rn] = T2H_4 (*(uint32_t*)memory);
mips_cpu->registers[rn] = T2H_4 (*(uint32_t*)memory);
return 4;
}
}
@ -911,12 +916,12 @@ mips_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
{
if (length == 8)
{
cpu->registers[rn] = T2H_8 (*(uint64_t*)memory);
mips_cpu->registers[rn] = T2H_8 (*(uint64_t*)memory);
return 8;
}
else
{
cpu->registers[rn] = (int32_t) T2H_4(*(uint32_t*)memory);
mips_cpu->registers[rn] = (int32_t) T2H_4(*(uint32_t*)memory);
return 4;
}
}
@ -930,7 +935,9 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length)
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
if (cpu->register_widths[rn] == 0)
struct mips_sim_cpu *mips_cpu = MIPS_SIM_CPU (cpu);
if (mips_cpu->register_widths[rn] == 0)
{
sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register fetch ignored)\n", rn);
return 0;
@ -939,17 +946,17 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length)
/* Any floating point register */
if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
{
if (cpu->register_widths[rn] == 32)
if (mips_cpu->register_widths[rn] == 32)
{
if (length == 8)
{
*(uint64_t*)memory =
H2T_8 ((uint32_t) (cpu->fgr[rn - FGR_BASE]));
H2T_8 ((uint32_t) (mips_cpu->fgr[rn - FGR_BASE]));
return 8;
}
else
{
*(uint32_t*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
*(uint32_t*)memory = H2T_4 (mips_cpu->fgr[rn - FGR_BASE]);
return 4;
}
}
@ -957,28 +964,28 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length)
{
if (length == 8)
{
*(uint64_t*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
*(uint64_t*)memory = H2T_8 (mips_cpu->fgr[rn - FGR_BASE]);
return 8;
}
else
{
*(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->fgr[rn - FGR_BASE]));
*(uint32_t*)memory = H2T_4 ((uint32_t)(mips_cpu->fgr[rn - FGR_BASE]));
return 4;
}
}
}
if (cpu->register_widths[rn] == 32)
if (mips_cpu->register_widths[rn] == 32)
{
if (length == 8)
{
*(uint64_t*)memory =
H2T_8 ((uint32_t) (cpu->registers[rn]));
H2T_8 ((uint32_t) (mips_cpu->registers[rn]));
return 8;
}
else
{
*(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->registers[rn]));
*(uint32_t*)memory = H2T_4 ((uint32_t)(mips_cpu->registers[rn]));
return 4;
}
}
@ -987,12 +994,12 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length)
if (length == 8)
{
*(uint64_t*)memory =
H2T_8 ((uint64_t) (cpu->registers[rn]));
H2T_8 ((uint64_t) (mips_cpu->registers[rn]));
return 8;
}
else
{
*(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->registers[rn]));
*(uint32_t*)memory = H2T_4 ((uint32_t)(mips_cpu->registers[rn]));
return 4;
}
}
@ -2532,55 +2539,66 @@ mips_core_signal (SIM_DESC sd,
void
mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
{
struct mips_sim_cpu *mips_cpu = MIPS_SIM_CPU (cpu);
ASSERT(cpu != NULL);
if (cpu->exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
if (mips_cpu->exc_suspended > 0)
sim_io_eprintf (sd, "Warning, nested exception triggered (%d)\n",
mips_cpu->exc_suspended);
PC = cia;
memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
cpu->exc_suspended = 0;
memcpy (mips_cpu->exc_trigger_registers, mips_cpu->registers,
sizeof (mips_cpu->exc_trigger_registers));
mips_cpu->exc_suspended = 0;
}
void
mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
{
struct mips_sim_cpu *mips_cpu = MIPS_SIM_CPU (cpu);
ASSERT(cpu != NULL);
if (cpu->exc_suspended > 0)
if (mips_cpu->exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
cpu->exc_suspended, exception);
mips_cpu->exc_suspended, exception);
memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
cpu->exc_suspended = exception;
memcpy (mips_cpu->exc_suspend_registers, mips_cpu->registers,
sizeof (mips_cpu->exc_suspend_registers));
memcpy (mips_cpu->registers, mips_cpu->exc_trigger_registers,
sizeof (mips_cpu->registers));
mips_cpu->exc_suspended = exception;
}
void
mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
{
struct mips_sim_cpu *mips_cpu = MIPS_SIM_CPU (cpu);
ASSERT(cpu != NULL);
if (exception == 0 && cpu->exc_suspended > 0)
if (exception == 0 && mips_cpu->exc_suspended > 0)
{
/* warn not for breakpoints */
if (cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
if (mips_cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
cpu->exc_suspended);
mips_cpu->exc_suspended);
}
else if (exception != 0 && cpu->exc_suspended > 0)
else if (exception != 0 && mips_cpu->exc_suspended > 0)
{
if (exception != cpu->exc_suspended)
if (exception != mips_cpu->exc_suspended)
sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
cpu->exc_suspended, exception);
mips_cpu->exc_suspended, exception);
memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
memcpy (mips_cpu->registers, mips_cpu->exc_suspend_registers,
sizeof (mips_cpu->registers));
}
else if (exception != 0 && cpu->exc_suspended == 0)
else if (exception != 0 && mips_cpu->exc_suspended == 0)
{
sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
}
cpu->exc_suspended = 0;
mips_cpu->exc_suspended = 0;
}

51
sim/mips/sim-main.h
View file

@ -20,6 +20,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
#define SIM_HAVE_COMMON_SIM_CPU
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
@ -171,20 +173,20 @@ typedef struct _pending_write_queue {
#ifndef PENDING_TRACE
#define PENDING_TRACE 0
#endif
#define PENDING_IN ((CPU)->pending.in)
#define PENDING_OUT ((CPU)->pending.out)
#define PENDING_TOTAL ((CPU)->pending.total)
#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
#define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
#define PENDING_IN (MIPS_SIM_CPU (CPU)->pending.in)
#define PENDING_OUT (MIPS_SIM_CPU (CPU)->pending.out)
#define PENDING_TOTAL (MIPS_SIM_CPU (CPU)->pending.total)
#define PENDING_SLOT_SIZE (MIPS_SIM_CPU (CPU)->pending.slot_size)
#define PENDING_SLOT_BIT (MIPS_SIM_CPU (CPU)->pending.slot_bit)
#define PENDING_SLOT_DELAY (MIPS_SIM_CPU (CPU)->pending.slot_delay)
#define PENDING_SLOT_DEST (MIPS_SIM_CPU (CPU)->pending.slot_dest)
#define PENDING_SLOT_VALUE (MIPS_SIM_CPU (CPU)->pending.slot_value)
/* Invalidate the pending write queue, all pending writes are
discarded. */
#define PENDING_INVALIDATE() \
memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
memset (&MIPS_SIM_CPU (CPU)->pending, 0, sizeof (MIPS_SIM_CPU (CPU)->pending))
/* Schedule a write to DEST for N cycles time. For 64 bit
destinations, schedule two writes. For floating point registers,
@ -258,12 +260,11 @@ typedef union {
#define SIM_STATE sim_cpu *cpu, address_word cia
#define SIM_ARGS CPU, cia
struct _sim_cpu {
struct mips_sim_cpu {
/* The following are internal simulator state variables: */
address_word dspc; /* delay-slot PC */
#define DSPC ((CPU)->dspc)
#define DSPC (MIPS_SIM_CPU (CPU)->dspc)
#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
#define FORBIDDEN_SLOT() { NIA = forbiddenslot32 (SD_); }
@ -273,8 +274,8 @@ struct _sim_cpu {
/* State of the simulator */
unsigned int state;
unsigned int dsstate;
#define STATE ((CPU)->state)
#define DSSTATE ((CPU)->dsstate)
#define STATE (MIPS_SIM_CPU (CPU)->state)
#define DSSTATE (MIPS_SIM_CPU (CPU)->dsstate)
/* Flags in the "state" variable: */
#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
@ -331,7 +332,7 @@ struct _sim_cpu {
unsigned_word registers[LAST_EMBED_REGNUM + 1];
int register_widths[NUM_REGS];
#define REGISTERS ((CPU)->registers)
#define REGISTERS (MIPS_SIM_CPU (CPU)->registers)
#define GPR (&REGISTERS[0])
#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
@ -409,7 +410,7 @@ struct _sim_cpu {
#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
unsigned_word c0_config_reg;
#define C0_CONFIG ((CPU)->c0_config_reg)
#define C0_CONFIG (MIPS_SIM_CPU (CPU)->c0_config_reg)
/* The following are pseudonyms for standard registers */
#define ZERO (REGISTERS[0])
@ -431,7 +432,7 @@ struct _sim_cpu {
#define NR_COP0_GPR 32
unsigned_word cop0_gpr[NR_COP0_GPR];
#define COP0_GPR ((CPU)->cop0_gpr)
#define COP0_GPR (MIPS_SIM_CPU (CPU)->cop0_gpr)
#define COP0_BADVADDR (COP0_GPR[8])
/* While space is allocated for the floating point registers in the
@ -441,17 +442,17 @@ struct _sim_cpu {
#define NR_FGR (32)
#define FGR_BASE FP0_REGNUM
fp_word fgr[NR_FGR];
#define FGR ((CPU)->fgr)
#define FGR (MIPS_SIM_CPU (CPU)->fgr)
/* Keep the current format state for each register: */
FP_formats fpr_state[32];
#define FPR_STATE ((CPU)->fpr_state)
#define FPR_STATE (MIPS_SIM_CPU (CPU)->fpr_state)
pending_write_queue pending;
/* The MDMX accumulator (used only for MDMX ASE). */
MDMX_accumulator acc;
#define ACC ((CPU)->acc)
#define ACC (MIPS_SIM_CPU (CPU)->acc)
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
read-write instructions. It is set when a linked load occurs. It
@ -460,7 +461,7 @@ struct _sim_cpu {
no longer be atomic. In particular, it is cleared by exception
return instructions. */
int llbit;
#define LLBIT ((CPU)->llbit)
#define LLBIT (MIPS_SIM_CPU (CPU)->llbit)
/* The HIHISTORY and LOHISTORY timestamps are used to ensure that
@ -468,13 +469,11 @@ struct _sim_cpu {
following operation is spotted. See mips.igen for more details. */
hilo_history hi_history;
#define HIHISTORY (&(CPU)->hi_history)
#define HIHISTORY (&MIPS_SIM_CPU (CPU)->hi_history)
hilo_history lo_history;
#define LOHISTORY (&(CPU)->lo_history)
sim_cpu_base base;
#define LOHISTORY (&MIPS_SIM_CPU (CPU)->lo_history)
};
#define MIPS_SIM_CPU(cpu) ((struct mips_sim_cpu *) CPU_ARCH_DATA (cpu))
extern void mips_sim_close (SIM_DESC sd, int quitting);
#define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__)