opcodes/
* ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
gas/
* testsuite/gas/ppc/byte_rev.d,
* testsuite/gas/ppc/byte_rev.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
opcodes/
* ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
gas/
* testsuite/gas/ppc/power10.s: New test.
* testsuite/gas/ppc/power10.d: Likewise.
* testsuite/gas/ppc/ppc.exp: Run it.
Now that ISA3.1 is out we can finish with the powerxx silliness.
bfd/
* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
renaming.
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
* powerpc.cc: Rename powerxx to power10 throughout.
include/
* elf/ppc64.h: Update comment.
* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Likewise.
* testsuite/ld-powerpc/tlsgd.d: Likewise.
* testsuite/ld-powerpc/tlsie.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power10" entry.
(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
* ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
PR 22699
opcodes * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
* sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
IMM0_8U case.
gas * config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to
IMM0_8S and add support for IMM0_8U.
* testsuite/gas/sh/sh4a.s: Add test of a logical insn using an
unsigned 8-bit immediate.
* testsuite/gas/sh/sh4a.d: Extended expected disassembly.
The MC68000/10 decodes the second operand of CMPI strictly as destination
operand, which disallows PC relative addressing, even though the insn
doesn't write to the operand. This restriction has only been lifted for
the MC68020+ and CPU32.
opcodes:
PR 25848
* m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
cmpi only on m68020up and cpu32.
gas:
PR 25848
* testsuite/gas/m68k/operands.s: Add tests for cmpi.
* testsuite/gas/m68k/operands.d: Update.
* testsuite/gas/m68k/op68000.d: Update for new error messages.
This patch implements the TSB instructions:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
tsb-csync-trace-synchronization-barrier
Since TSB and PSB both use the same (and only) argument "CSYNC", this patch
reuses it for TSB. However, the same argument would imply different value
for CRm:Op2 which are anyway fixed values, so I have diverted the
inserter/extracter function to dummy versions instead of the "hint" version.
The operand checker part still uses the existing infratructure for
AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly.
gas/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_barrier_psb): Update error messages
to include TSB.
* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
* testsuite/gas/aarch64/system.d: Update.
opcodes/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_none): New.
* aarch64-asm.h (ins_none): New declaration.
* aarch64-dis.c (aarch64_ext_none): New.
* aarch64-dis.h (ext_none): New declaration.
* aarch64-opc.c (aarch64_print_operand): Update case for
AARCH64_OPND_BARRIER_PSB.
* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
(AARCH64_OPERANDS): Update inserter/extracter for
AARCH64_OPND_BARRIER_PSB to use new dummy functions.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
There are a few instruction in AArch64 that are in the HINT space. Any of
these instructions should be accepted by the assembler/disassembler at any
architecture version. This patch fixes the existing instructions that are
not behaving accordingly.
I have used all of the instructions mentioned in the following to make the
changes:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
hint-hint-instruction
gas/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/bti.d: Update -march option.
* testsuite/gas/aarch64/illegal-bti.d: Remove.
* testsuite/gas/aarch64/illegal-bti.l: Remove.
* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
opcodes/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
(aarch64_feature_ras, RAS): Likewise.
(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
autiaz, autiasp, autibz, autibsp to be CORE_INSN.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
VDUP (neon) instructions can be conditional, but this is not taken into
account in the current master. This commit fixes that by i) fixing the
VDUP instruction masks and ii) adding logic for disassembling
conditional neon instructions.
opcodes * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
(print_insn_neon): Support disassembly of conditional
instructions.
binutils* testsuite/binutils-all/arm/vdup-cond.d: New test for testing that
conditional VDUP instructions are disassembled correctly.
* testsuite/binutils-all/arm/vdup-cond.s: New file used by
vdup-cond.d.
* testsuite/binutils-all/arm/vdup-thumb.d: New test for testing
that VDUP instructions (which are conditional in A32) can be
disassembled in thumb mode.
* testsuite/binutils-all/arm/vdup-cond.s: New file used by
vdup-thumb.d.
Add support for the JMP32 class of eBPF instructions.
cpu/ChangeLog
* bpf.cpu (define-cond-jump-insn): Renamed from djci.
(dcji) New version with support for JMP32
gas/ChangeLog
* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
* testsuite/gas/bpf/jump32.s: New file.
* testsuite/gas/bpf/jump32.d: Likewise.
opcodes/ChangeLog
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Regenerate.
* bpf-opc.h: Likewise.
This patch also had some problems. Calculation of maxlen was wrong,
and the insn arg loop needed rearranging to work with a correct length.
* disassemble.h (opcodes_assert): Declare.
(OPCODES_ASSERT): Define.
* disassemble.c: Don't include assert.h. Include opintl.h.
(opcodes_assert): New function.
* h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
(bfd_h8_disassemble): Reduce size of data array. Correctly
calculate maxlen. Omit insn decoding when insn length exceeds
maxlen. Exit from nibble loop when looking for E, before
accessing next data byte. Move processing of E outside loop.
Replace tests of maxlen in loop with assertions.
git commit beea5cc1bc fixed one use of an uninitialised value but
ignored another one a few lines later.
* arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
* arc-dis.c (find_format): Use ISO C string concatenation rather
than line continuation within a string. Don't access needs_limm
before testing opcode != NULL.
git commit d1e304bc27 was aimed at stopping uninitialised memory
access to the index_offset array. Unfortunately that patch resulted
in a different array being uninitialised for all instructions with
more than two arguments.
* ns32k-dis.c (print_insn_arg): Update comment.
(print_insn_ns32k): Reduce size of index_offset array, and
initialize, passing -1 to print_insn_arg for args that are not
an index. Don't exit arg loop early. Abort on bad arg number.
* nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
Initialize parts of buffer not written when handling a possible
2-byte insn at end of section. Don't attempt decoding of such
an insn by the 4-byte machinery.
We shouldn't really decode a 2-byte left-over at the end of a section
as if the section contains two more bytes of zeros. Not that it
matters very much, but this patch tidies the corner case.
* ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
partially filled buffer. Prevent lookup of 4-byte insns when
only VLE 2-byte insns are possible due to section size. Print
".word" rather than ".long" for 2-byte leftovers.
Since i386-opc.tbl contains '\' to avoid very long lines and i386-gen
requires that each instruction must be in one line, also pass -P to
$(CPP) to inhibit generation of linemarkers in the output from the
preprocessor to support i386-gen.
* Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
* Makefile.in: Regenerated.
These all follow an almost common pattern, again with the exception of
being commutative, which can be easily taken care of.
Note that, as an intended side effect (and in fact one of the reason to
introduce templates), AVX long-form pseudo-ops get introduced alongside
the already existing AVX512 ones.
In order to reduce redundancy as well as the chance of things going out
of sync (see a later patch for an example), make the opcode table
generator capable of recognizing and expanding templated templates. Use
the new capability for compacting the general purpose conditional insns.
Presumably as a result of various changes over the last several months,
and - for some of them - with a generalization of logic in
match_mem_size() plus mirroring of this generalization into the
broadcast handling logic of check_VecOperands(), various register-only
templates can be foled into their respective memory forms. This in
particular then also allows dropping a few more instances of IgnoreSize.
Even after commit dc2be329b9 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.
To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.
Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.
Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.
Convert VexW= again to their respective VexW* on lines touched anyway.
