Power10 SIMD permute class operations
opcodes/ * ppc-opc.c (insert_imm32, extract_imm32): New functions. (insert_xts, extract_xts): New functions. (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define. (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define. (VXRC_MASK, VXSH_MASK): Define. (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx, vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx, vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx, vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx, vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq. (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb, xxblendvh, xxblendvw, xxblendvd, xxpermx. gas/ * testsuite/gas/ppc/simd_perm.d, * testsuite/gas/ppc/simd_perm.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
This commit is contained in:
Alan Modra
parent
c7d7aea2f5
commit
6edbfd3beb
6 changed files with 226 additions and 3 deletions
|
|
@ -1,3 +1,9 @@
|
|||
2020-05-11 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* testsuite/gas/ppc/simd_perm.d,
|
||||
* testsuite/gas/ppc/simd_perm.s: New test.
|
||||
* testsuite/gas/ppc/ppc.exp: Run it.
|
||||
|
||||
2020-05-11 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* testsuite/gas/ppc/int128.d,
|
||||
|
|
|
|||
|
|
@ -135,3 +135,4 @@ run_dump_test "byte_rev"
|
|||
run_dump_test "vec_mul"
|
||||
run_dump_test "vsx_32byte"
|
||||
run_dump_test "int128"
|
||||
run_dump_test "simd_perm"
|
||||
|
|
|
|||
53
gas/testsuite/gas/ppc/simd_perm.d
Normal file
53
gas/testsuite/gas/ppc/simd_perm.d
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
#as: -mpower10
|
||||
#objdump: -dr -Mpower10
|
||||
#name: SIMD permute
|
||||
|
||||
.*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+0 <_start>:
|
||||
.*: (10 01 10 d8|d8 10 01 10) vextdubvlx v0,v1,v2,r3
|
||||
.*: (10 85 31 d9|d9 31 85 10) vextdubvrx v4,v5,v6,r7
|
||||
.*: (11 09 52 da|da 52 09 11) vextduhvlx v8,v9,v10,r11
|
||||
.*: (11 8d 73 db|db 73 8d 11) vextduhvrx v12,v13,v14,r15
|
||||
.*: (12 11 94 dc|dc 94 11 12) vextduwvlx v16,v17,v18,r19
|
||||
.*: (12 95 b5 dd|dd b5 95 12) vextduwvrx v20,v21,v22,r23
|
||||
.*: (13 19 d6 de|de d6 19 13) vextddvlx v24,v25,v26,r27
|
||||
.*: (13 9d f7 df|df f7 9d 13) vextddvrx v28,v29,v30,r31
|
||||
.*: (10 01 12 0f|0f 12 01 10) vinsblx v0,r1,r2
|
||||
.*: (10 64 2b 0f|0f 2b 64 10) vinsbrx v3,r4,r5
|
||||
.*: (10 c7 42 4f|4f 42 c7 10) vinshlx v6,r7,r8
|
||||
.*: (11 2a 5b 4f|4f 5b 2a 11) vinshrx v9,r10,r11
|
||||
.*: (11 8d 72 8f|8f 72 8d 11) vinswlx v12,r13,r14
|
||||
.*: (11 f0 8b 8f|8f 8b f0 11) vinswrx v15,r16,r17
|
||||
.*: (12 53 a2 cf|cf a2 53 12) vinsdlx v18,r19,r20
|
||||
.*: (12 b6 bb cf|cf bb b6 12) vinsdrx v21,r22,r23
|
||||
.*: (13 19 d0 0f|0f d0 19 13) vinsbvlx v24,r25,v26
|
||||
.*: (13 7c e9 0f|0f e9 7c 13) vinsbvrx v27,r28,v29
|
||||
.*: (13 df 00 4f|4f 00 df 13) vinshvlx v30,r31,v0
|
||||
.*: (10 22 19 4f|4f 19 22 10) vinshvrx v1,r2,v3
|
||||
.*: (10 85 30 8f|8f 30 85 10) vinswvlx v4,r5,v6
|
||||
.*: (10 e8 49 8f|8f 49 e8 10) vinswvrx v7,r8,v9
|
||||
.*: (11 4c 58 cf|cf 58 4c 11) vinsw v10,r11,12
|
||||
.*: (11 a3 71 cf|cf 71 a3 11) vinsd v13,r14,3
|
||||
.*: (11 f0 89 56|56 89 f0 11) vsldbi v15,v16,v17,5
|
||||
.*: (12 53 a3 d6|d6 a3 53 12) vsrdbi v18,v19,v20,7
|
||||
.*: (05 00 01 23|23 01 00 05) xxspltiw vs63,19088743
|
||||
.*: (83 e7 45 67|67 45 e7 83)
|
||||
.*: (05 00 89 ab|ab 89 00 05) xxsplti32dx vs62,1,2309737967
|
||||
.*: (83 c3 cd ef|ef cd c3 83)
|
||||
.*: (05 00 01 23|23 01 00 05) xxspltidp vs61,19088743
|
||||
.*: (83 a5 45 67|67 45 a5 83)
|
||||
.*: (f3 9f c2 d1|d1 c2 9f f3) lxvkq vs60,24
|
||||
.*: (05 00 00 00|00 00 00 05) xxblendvb vs59,vs58,vs57,vs56
|
||||
.*: (87 7a ce 0f|0f ce 7a 87)
|
||||
.*: (05 00 00 00|00 00 00 05) xxblendvh vs55,vs54,vs53,vs52
|
||||
.*: (86 f6 ad 1f|1f ad f6 86)
|
||||
.*: (05 00 00 00|00 00 00 05) xxblendvw vs51,vs50,vs49,vs48
|
||||
.*: (86 72 8c 2f|2f 8c 72 86)
|
||||
.*: (05 00 00 00|00 00 00 05) xxblendvd vs47,vs46,vs45,vs44
|
||||
.*: (85 ee 6b 3f|3f 6b ee 85)
|
||||
.*: (05 00 00 07|07 00 00 05) xxpermx vs43,vs42,vs41,vs40,7
|
||||
.*: (89 6a 4a 0f|0f 4a 6a 89)
|
||||
37
gas/testsuite/gas/ppc/simd_perm.s
Normal file
37
gas/testsuite/gas/ppc/simd_perm.s
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
.text
|
||||
_start:
|
||||
vextdubvlx 0,1,2,3
|
||||
vextdubvrx 4,5,6,7
|
||||
vextduhvlx 8,9,10,11
|
||||
vextduhvrx 12,13,14,15
|
||||
vextduwvlx 16,17,18,19
|
||||
vextduwvrx 20,21,22,23
|
||||
vextddvlx 24,25,26,27
|
||||
vextddvrx 28,29,30,31
|
||||
vinsblx 0,1,2
|
||||
vinsbrx 3,4,5
|
||||
vinshlx 6,7,8
|
||||
vinshrx 9,10,11
|
||||
vinswlx 12,13,14
|
||||
vinswrx 15,16,17
|
||||
vinsdlx 18,19,20
|
||||
vinsdrx 21,22,23
|
||||
vinsbvlx 24,25,26
|
||||
vinsbvrx 27,28,29
|
||||
vinshvlx 30,31,0
|
||||
vinshvrx 1,2,3
|
||||
vinswvlx 4,5,6
|
||||
vinswvrx 7,8,9
|
||||
vinsw 10,11,12
|
||||
vinsd 13,14,3
|
||||
vsldbi 15,16,17,5
|
||||
vsrdbi 18,19,20,7
|
||||
xxspltiw 63,0x01234567
|
||||
xxsplti32dx 62,1,0x89abcdef
|
||||
xxspltidp 61,0x01234567
|
||||
lxvkq 60,24
|
||||
xxblendvb 59,58,57,56
|
||||
xxblendvh 55,54,53,52
|
||||
xxblendvw 51,50,49,48
|
||||
xxblendvd 47,46,45,44
|
||||
xxpermx 43,42,41,40,7
|
||||
|
|
@ -1,3 +1,18 @@
|
|||
2020-05-11 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* ppc-opc.c (insert_imm32, extract_imm32): New functions.
|
||||
(insert_xts, extract_xts): New functions.
|
||||
(IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
|
||||
(P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
|
||||
(VXRC_MASK, VXSH_MASK): Define.
|
||||
(powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
|
||||
vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
|
||||
vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
|
||||
vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
|
||||
vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
|
||||
(prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
|
||||
xxblendvh, xxblendvw, xxblendvd, xxpermx.
|
||||
|
||||
2020-05-11 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
|
||||
|
|
|
|||
|
|
@ -643,6 +643,25 @@ extract_nsi34 (uint64_t insn,
|
|||
return -value;
|
||||
}
|
||||
|
||||
/* The split IMM32 field in a vector splat insn. */
|
||||
|
||||
static uint64_t
|
||||
insert_imm32 (uint64_t insn,
|
||||
int64_t value,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
const char **errmsg ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return insn | ((value & 0xffff0000) << 16) | (value & 0xffff);
|
||||
}
|
||||
|
||||
static int64_t
|
||||
extract_imm32 (uint64_t insn,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
int *invalid ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return (insn & 0xffff) | ((insn >> 16) & 0xffff0000);
|
||||
}
|
||||
|
||||
/* The R field in an 8-byte prefix instruction when there are restrictions
|
||||
between R's value and the RA value (ie, they cannot both be non zero). */
|
||||
|
||||
|
|
@ -1613,6 +1632,25 @@ extract_xtp (uint64_t insn,
|
|||
return ((insn >> (21 - 5)) & 0x20) | ((insn >> 21) & 0x1e);
|
||||
}
|
||||
|
||||
/* The split XT field in a vector splat insn. */
|
||||
|
||||
static uint64_t
|
||||
insert_xts (uint64_t insn,
|
||||
int64_t value,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
const char **errmsg ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return insn | ((value & 0x1f) << 21) | ((value & 0x20) << (16 - 5));
|
||||
}
|
||||
|
||||
static int64_t
|
||||
extract_xts (uint64_t insn,
|
||||
ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
||||
int *invalid ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return ((insn >> (16 - 5)) & 0x20) | ((insn >> 21) & 0x1f);
|
||||
}
|
||||
|
||||
static uint64_t
|
||||
insert_dm (uint64_t insn,
|
||||
int64_t value,
|
||||
|
|
@ -2202,9 +2240,21 @@ const struct powerpc_operand powerpc_operands[] =
|
|||
{ UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34,
|
||||
PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
|
||||
|
||||
/* The IMM32 field in a vector splat immediate prefix instruction. */
|
||||
#define IMM32 NSI34 + 1
|
||||
{ 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0},
|
||||
|
||||
/* The UIM field in a vector permute extended prefix instruction. */
|
||||
#define UIM3 IMM32 + 1
|
||||
{ 0x7, 32, NULL, NULL, 0},
|
||||
|
||||
/* The IX field in xxsplti32dx. */
|
||||
#define IX UIM3 + 1
|
||||
{ 0x1, 17, NULL, NULL, 0 },
|
||||
|
||||
/* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
|
||||
unsigned imediate */
|
||||
#define DUIS NSI34 + 1
|
||||
#define DUIS IX + 1
|
||||
#define BHRBE DUIS
|
||||
{ 0x3ff, 11, NULL, NULL, 0 },
|
||||
|
||||
|
|
@ -2524,6 +2574,7 @@ const struct powerpc_operand powerpc_operands[] =
|
|||
#define EVUIMM SH
|
||||
/* The FC field in an atomic X form instruction. */
|
||||
#define FC SH
|
||||
#define UIM5 SH
|
||||
{ 0x1f, 11, NULL, NULL, 0 },
|
||||
|
||||
#define EVUIMM_LT8 SH + 1
|
||||
|
|
@ -2679,8 +2730,12 @@ const struct powerpc_operand powerpc_operands[] =
|
|||
#define PS SIX + 1
|
||||
{ 0x1, 9, NULL, NULL, 0 },
|
||||
|
||||
/* The SH field in a vector shift double by bit immediate instruction. */
|
||||
#define SH3 PS + 1
|
||||
{ 0x7, 6, NULL, NULL, 0 },
|
||||
|
||||
/* The SHB field in a VA form instruction. */
|
||||
#define SHB PS + 1
|
||||
#define SHB SH3 + 1
|
||||
{ 0xf, 6, NULL, NULL, 0 },
|
||||
|
||||
/* The other UIMM field in a half word EVX form instruction. */
|
||||
|
|
@ -2840,8 +2895,11 @@ const struct powerpc_operand powerpc_operands[] =
|
|||
#define XTP XSQ6 + 1
|
||||
{ 0x3e, PPC_OPSHIFT_INV, insert_xtp, extract_xtp, PPC_OPERAND_VSR },
|
||||
|
||||
#define XTS XTP + 1
|
||||
{ 0x3f, PPC_OPSHIFT_INV, insert_xts, extract_xts, PPC_OPERAND_VSR },
|
||||
|
||||
/* The XT field in a plxv instruction. Runs into the OP field. */
|
||||
#define XTOP XTP + 1
|
||||
#define XTOP XTS + 1
|
||||
{ 0x3f, 21, NULL, NULL, PPC_OPERAND_VSR },
|
||||
|
||||
/* The XA field in an XX3 form instruction. This is split. */
|
||||
|
|
@ -2926,6 +2984,9 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
|
|||
/* Prefix insn, eight byte load/store form 8LS. */
|
||||
#define P8LS (PREFIX_OP | PREFIX_FORM (0))
|
||||
|
||||
/* Prefix insn, eight byte register to register form 8RR. */
|
||||
#define P8RR (PREFIX_OP | PREFIX_FORM (1))
|
||||
|
||||
/* Prefix insn, modified load/store form MLS. */
|
||||
#define PMLS (PREFIX_OP | PREFIX_FORM (2))
|
||||
|
||||
|
|
@ -2938,6 +2999,15 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
|
|||
/* The same as P_D_MASK, but with the RA and PCREL fields specified. */
|
||||
#define P_DRAPCREL_MASK (P_D_MASK | PCREL_MASK | RA_MASK)
|
||||
|
||||
/* Mask for prefix vector permute insns. */
|
||||
#define P_XX4_MASK (PREFIX_MASK | XX4_MASK)
|
||||
#define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32))
|
||||
|
||||
/* Vector splat immediate op. */
|
||||
#define VSOP(op, xop) (OP (op) | (xop << 17))
|
||||
#define P_VS_MASK ((-1ULL << 48) | VSOP (0x3f, 0xf))
|
||||
#define P_VSI_MASK ((-1ULL << 48) | VSOP (0x3f, 0xe))
|
||||
|
||||
/* The main opcode combined with a trap code in the TO field of a D
|
||||
form instruction. Used for extended mnemonics for the trap
|
||||
instructions. */
|
||||
|
|
@ -3316,6 +3386,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
|
|||
/* A VX_MASK for instructions using a BF field. */
|
||||
#define VXBF_MASK (VX_MASK | (3 << 21))
|
||||
|
||||
/* A VX_MASK for instructions with an RC field. */
|
||||
#define VXRC_MASK (VX_MASK & ~(0x1f << 6))
|
||||
|
||||
/* A VX_MASK for instructions with a SH field. */
|
||||
#define VXSH_MASK (VX_MASK & ~(0x7 << 6))
|
||||
|
||||
/* A VA form instruction. */
|
||||
#define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f))
|
||||
|
||||
|
|
@ -3923,21 +3999,31 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
|
||||
{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vinsbvlx", VX (4, 15), VX_MASK, POWER10, 0, {VD, RA, VB}},
|
||||
{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
|
||||
{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
|
||||
{"vsldbi", VX (4, 22), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}},
|
||||
{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
|
||||
{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
|
||||
{"vextdubvlx", VX (4, 24), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
|
||||
{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
|
||||
{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"vextdubvrx", VX (4, 25), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
|
||||
{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
|
||||
{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"vextduhvlx", VX (4, 26), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
|
||||
{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
|
||||
{"vextduhvrx", VX (4, 27), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
|
||||
{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
|
||||
{"vextduwvlx", VX (4, 28), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
|
||||
{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
|
||||
{"vextduwvrx", VX (4, 29), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
|
||||
{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
|
||||
{"vextddvlx", VX (4, 30), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
|
||||
{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
|
||||
{"vextddvrx", VX (4, 31), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
|
||||
{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
|
||||
{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
|
||||
{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
|
||||
|
|
@ -4000,6 +4086,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
|
||||
{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vinshvlx", VX (4, 79), VX_MASK, POWER10, 0, {VD, RA, VB}},
|
||||
{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
|
||||
{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
|
||||
|
|
@ -4020,6 +4107,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vdivuw", VX (4, 139), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||
{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vinswvlx", VX (4, 143), VX_MASK, POWER10, 0, {VD, RA, VB}},
|
||||
{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
|
||||
{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
|
||||
{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
|
|
@ -4034,6 +4122,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vmuloud", VX (4, 200), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||
{"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||
{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vinsw", VX (4, 207), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}},
|
||||
{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
|
|
@ -4049,6 +4138,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vdivsq", VX (4, 267), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||
{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vinsbvrx", VX (4, 271), VX_MASK, POWER10, 0, {VD, RA, VB}},
|
||||
{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
|
||||
{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
|
||||
|
|
@ -4065,6 +4155,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
|
||||
{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vinshvrx", VX (4, 335), VX_MASK, POWER10, 0, {VD, RA, VB}},
|
||||
{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
|
|
@ -4081,6 +4172,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||
{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vinswvrx", VX (4, 399), VX_MASK, POWER10, 0, {VD, RA, VB}},
|
||||
{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
||||
|
|
@ -4093,6 +4185,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
|
||||
{"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||
{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vinsd", VX (4, 463), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}},
|
||||
{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
|
|
@ -4122,11 +4215,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
|
||||
{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
|
||||
{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
|
||||
{"vinsblx", VX (4, 527), VX_MASK, POWER10, 0, {VD, RA, RB}},
|
||||
{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
|
||||
{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
|
||||
{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
|
||||
{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
|
||||
{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
|
||||
{"vsrdbi", VX (4, 534), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}},
|
||||
{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
|
||||
{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RAB}},
|
||||
{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
|
||||
|
|
@ -4166,6 +4261,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
|
||||
{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
|
||||
{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
|
||||
{"vinshlx", VX (4, 591), VX_MASK, POWER10, 0, {VD, RA, RB}},
|
||||
{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
|
||||
{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
|
||||
{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
|
||||
|
|
@ -4196,6 +4292,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
|
||||
{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
|
||||
{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
|
||||
{"vinswlx", VX (4, 655), VX_MASK, POWER10, 0, {VD, RA, RB}},
|
||||
{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
|
||||
{"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
|
||||
{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
|
||||
|
|
@ -4257,6 +4354,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
|
||||
{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
|
||||
{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
|
||||
{"vinsdlx", VX (4, 719), VX_MASK, POWER10, 0, {VD, RA, RB}},
|
||||
{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
|
||||
{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
|
||||
{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
|
||||
|
|
@ -4337,6 +4435,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
|
||||
{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
|
||||
{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||
{"vinsbrx", VX (4, 783), VX_MASK, POWER10, 0, {VD, RA, RB}},
|
||||
{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
|
||||
{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
|
||||
|
|
@ -4377,6 +4476,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
|
||||
{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
|
||||
{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
|
||||
{"vinshrx", VX (4, 847), VX_MASK, POWER10, 0, {VD, RA, RB}},
|
||||
{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
|
|
@ -4395,6 +4495,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vdivesw", VX (4, 907), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||
{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
|
||||
{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
|
||||
{"vinswrx", VX (4, 911), VX_MASK, POWER10, 0, {VD, RA, RB}},
|
||||
{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
||||
|
|
@ -4408,6 +4509,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"vdivesd", VX (4, 971), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||
{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
|
||||
{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
|
||||
{"vinsdrx", VX (4, 975), VX_MASK, POWER10, 0, {VD, RA, RB}},
|
||||
{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||
|
|
@ -7643,6 +7745,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
|
||||
{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
|
||||
{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
|
||||
{"lxvkq", XVA(60,360,31), XVA_MASK&~1, POWER10, PPCVLE, {XT6, UIM5}},
|
||||
{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
|
||||
{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
|
||||
{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
|
||||
|
|
@ -8095,7 +8198,15 @@ const struct powerpc_opcode prefix_opcodes[] = {
|
|||
{"paddi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, SI34, PCREL0}},
|
||||
{"psubi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, NSI34, PCREL0}},
|
||||
{"pla", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
|
||||
{"xxsplti32dx", P8RR|VSOP(32,0), P_VSI_MASK, POWER10, 0, {XTS, IX, IMM32}},
|
||||
{"xxspltidp", P8RR|VSOP(32,2), P_VS_MASK, POWER10, 0, {XTS, IMM32}},
|
||||
{"xxspltiw", P8RR|VSOP(32,3), P_VS_MASK, POWER10, 0, {XTS, IMM32}},
|
||||
{"plwz", PMLS|OP(32), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
|
||||
{"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
|
||||
{"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
|
||||
{"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
|
||||
{"xxblendvd", P8RR|XX4(33,3), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
|
||||
{"xxpermx", P8RR|XX4(34,0), P_UXX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM3}},
|
||||
{"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
|
||||
{"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
|
||||
{"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue