Fix a small set of Z80 problems.
PR 25641 PR 25668 PR 25633 gas Fix disassembling ED+A4/AC/B4/BC opcodes. Fix assembling lines containing colonless label and instruction with first operand inside parentheses. Fix registration of unsupported by target CPU registers. * config/tc-z80.c: See above. * config/tc-z80.h: See above. * testsuite/gas/z80/colonless.d: Update test. * testsuite/gas/z80/colonless.s: Likewise. * testsuite/gas/z80/ez80_adl_all.d: Likewise. * testsuite/gas/z80/ez80_unsup_regs.d: Likewise. * testsuite/gas/z80/ez80_z80_all.d: Likewise. * testsuite/gas/z80/gbz80_unsup_regs.d: Likewise. * testsuite/gas/z80/r800_unsup_regs.d: Likewise. * testsuite/gas/z80/unsup_regs.s: Likewise. * testsuite/gas/z80/z180_unsup_regs.d: Likewise. * testsuite/gas/z80/z80.exp: Likewise. * testsuite/gas/z80/z80_strict_unsup_regs.d: Likewise. * testsuite/gas/z80/z80_unsup_regs.d: Likewise. * testsuite/gas/z80/z80n_unsup_regs.d: Likewise. opcodes * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
This commit is contained in:
Sergey Belyashov
Nick Clifton
parent
ecbbbdba71
commit
68e52bc7ec
16 changed files with 436 additions and 175 deletions
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@ -155,7 +155,7 @@ struct match_info
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static const struct match_info
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match_cpu_table [] =
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{
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{"z80", INS_Z80, 0, 0, "Zilog Z80 (+infc+xyhl)" },
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{"z80", INS_Z80, 0, 0, "Zilog Z80" },
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{"ez80", INS_EZ80, 0, 0, "Zilog eZ80" },
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{"gbz80", INS_GBZ80, INS_UNDOC|INS_UNPORT, 0, "GameBoy Z80" },
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{"r800", INS_R800, INS_UNPORT, 0, "Ascii R800" },
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@ -428,6 +428,7 @@ struct reg_entry
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{
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const char* name;
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int number;
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int isa;
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};
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#define R_STACKABLE (0x80)
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#define R_ARITH (0x40)
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@ -457,28 +458,28 @@ struct reg_entry
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static const struct reg_entry regtable[] =
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{
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{"a", REG_A },
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{"af", REG_AF },
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{"b", REG_B },
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{"bc", REG_BC },
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{"c", REG_C },
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{"d", REG_D },
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{"de", REG_DE },
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{"e", REG_E },
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{"f", REG_F },
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{"h", REG_H },
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{"hl", REG_HL },
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{"i", REG_I },
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{"ix", REG_IX },
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{"ixh",REG_H | R_IX },
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{"ixl",REG_L | R_IX },
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{"iy", REG_IY },
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{"iyh",REG_H | R_IY },
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{"iyl",REG_L | R_IY },
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{"l", REG_L },
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{"mb", REG_MB },
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{"r", REG_R },
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{"sp", REG_SP },
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{"a", REG_A, INS_ALL },
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{"af", REG_AF, INS_ALL },
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{"b", REG_B, INS_ALL },
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{"bc", REG_BC, INS_ALL },
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{"c", REG_C, INS_ALL },
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{"d", REG_D, INS_ALL },
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{"de", REG_DE, INS_ALL },
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{"e", REG_E, INS_ALL },
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{"f", REG_F, INS_IN_F_C | INS_Z80N | INS_R800 },
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{"h", REG_H, INS_ALL },
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{"hl", REG_HL, INS_ALL },
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{"i", REG_I, INS_NOT_GBZ80 },
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{"ix", REG_IX, INS_NOT_GBZ80 },
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{"ixh", REG_H | R_IX, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N },
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{"ixl", REG_L | R_IX, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N },
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{"iy", REG_IY, INS_NOT_GBZ80 },
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{"iyh", REG_H | R_IY, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N },
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{"iyl", REG_L | R_IY, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N },
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{"l", REG_L, INS_ALL },
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{"mb", REG_MB, INS_EZ80 },
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{"r", REG_R, INS_NOT_GBZ80 },
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{"sp", REG_SP, INS_ALL },
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} ;
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#define BUFLEN 8 /* Large enough for any keyword. */
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@ -499,6 +500,8 @@ md_begin (void)
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reg.X_add_symbol = reg.X_op_symbol = 0;
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for ( i = 0 ; i < ARRAY_SIZE ( regtable ) ; ++i )
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{
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if (regtable[i].isa && !(regtable[i].isa & ins_ok))
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continue;
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reg.X_add_number = regtable[i].number;
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k = strlen ( regtable[i].name );
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buf[k] = 0;
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@ -615,7 +618,7 @@ z80_start_line_hook (void)
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break;
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}
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}
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/* Check for <label>[:] [.](EQU|DEFL) <value>. */
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/* Check for <label>[:] =|([.](EQU|DEFL)) <value>. */
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if (is_name_beginner (*input_line_pointer))
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{
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char *name;
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@ -625,20 +628,9 @@ z80_start_line_hook (void)
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line_start = input_line_pointer;
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if (ignore_input ())
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return 0;
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c = get_symbol_name (&name);
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rest = input_line_pointer + 1;
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if (ISSPACE (c) && colonless_labels)
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{
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if (c == '\n')
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{
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bump_line_counters ();
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LISTING_NEWLINE ();
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}
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c = ':';
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}
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if (*rest == ':')
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if (c == ':' && *rest == ':')
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{
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/* remove second colon if SDCC compatibility enabled */
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if (sdcc_compat)
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@ -646,15 +638,20 @@ z80_start_line_hook (void)
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++rest;
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}
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rest = (char*)skip_space (rest);
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if (*rest == '.')
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++rest;
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if (strncasecmp (rest, "EQU", 3) == 0)
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len = 3;
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else if (strncasecmp (rest, "DEFL", 4) == 0)
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len = 4;
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if (*rest == '=')
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len = (rest[1] == '=') ? 2 : 1;
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else
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len = 0;
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if (len && (!ISALPHA (rest[len])))
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{
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if (*rest == '.')
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++rest;
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if (strncasecmp (rest, "EQU", 3) == 0)
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len = 3;
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else if (strncasecmp (rest, "DEFL", 4) == 0)
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len = 4;
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else
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len = 0;
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}
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if (len && (len <= 2 || !ISALPHA (rest[len])))
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{
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/* Handle assignment here. */
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if (line_start[-1] == '\n')
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@ -664,7 +661,17 @@ z80_start_line_hook (void)
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}
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input_line_pointer = rest + len - 1;
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/* Allow redefining with "DEFL" (len == 4), but not with "EQU". */
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equals (name, len == 4);
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switch (len)
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{
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case 1: /* label = expr */
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case 4: /* label DEFL expr */
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equals (name, 1);
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break;
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case 2: /* label == expr */
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case 3: /* label EQU expr */
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equals (name, 0);
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break;
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}
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return 1;
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}
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else
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@ -1011,20 +1018,20 @@ parse_exp (const char *s, expressionS *op)
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/* Condition codes, including some synonyms provided by HiTech zas. */
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static const struct reg_entry cc_tab[] =
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{
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{ "age", 6 << 3 },
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{ "alt", 7 << 3 },
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{ "c", 3 << 3 },
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{ "di", 4 << 3 },
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{ "ei", 5 << 3 },
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{ "lge", 2 << 3 },
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{ "llt", 3 << 3 },
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{ "m", 7 << 3 },
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{ "nc", 2 << 3 },
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{ "nz", 0 << 3 },
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{ "p", 6 << 3 },
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{ "pe", 5 << 3 },
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{ "po", 4 << 3 },
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{ "z", 1 << 3 },
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{ "age", 6 << 3, INS_ALL },
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{ "alt", 7 << 3, INS_ALL },
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{ "c", 3 << 3, INS_ALL },
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{ "di", 4 << 3, INS_ALL },
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{ "ei", 5 << 3, INS_ALL },
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{ "lge", 2 << 3, INS_ALL },
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{ "llt", 3 << 3, INS_ALL },
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{ "m", 7 << 3, INS_ALL },
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{ "nc", 2 << 3, INS_ALL },
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{ "nz", 0 << 3, INS_ALL },
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{ "p", 6 << 3, INS_ALL },
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{ "pe", 5 << 3, INS_ALL },
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{ "po", 4 << 3, INS_ALL },
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{ "z", 1 << 3, INS_ALL },
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} ;
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/* Parse condition code. */
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@ -3811,6 +3818,12 @@ tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED , fixS *fixp)
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return reloc;
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}
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int
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z80_tc_labels_without_colon (void)
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{
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return colonless_labels;
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}
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int
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z80_tc_label_is_local (const char *name)
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{
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@ -96,6 +96,9 @@ extern void z80_cons_fix_new (fragS *, int, int, expressionS *);
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well, but it is cleaner to handle that in tc-z80.c. */
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#define SINGLE_QUOTE_STRINGS
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#define LABELS_WITHOUT_COLONS (z80_tc_labels_without_colon())
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extern int z80_tc_labels_without_colon (void);
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/* An `.lcomm' directive with no explicit alignment parameter will
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use this macro to set P2VAR to the alignment that a request for
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SIZE bytes will have. The alignment is expressed as a power of
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@ -7,9 +7,9 @@
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Disassembly of section \.text:
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00000000 <start>:
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0+0 <start>:
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[ ]+0:[ ]+3e 00[ ]+ld a,0x00
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[ ]+2:[ ]+28 0c[ ]+jr z,0x0010
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[ ]+2:[ ]+28 0d[ ]+jr z,0x0011
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[ ]+4:[ ]+3e 01[ ]+ld a,0x01
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[ ]+6:[ ]+3e 02[ ]+ld a,0x02
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[ ]+8:[ ]+3e 03[ ]+ld a,0x03
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@ -17,5 +17,9 @@ Disassembly of section \.text:
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[ ]+c:[ ]+18 f4[ ]+jr 0x0002
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[ ]+e:[ ]+18 f6[ ]+jr 0x0006
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00000010 <finish>:
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[ ]+10:[ ]+c9[ ]+ret
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0+10 <label>:
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[ ]+10:[ ]+e9[ ]+jp \(hl\)
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0+11 <finish>:
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[ ]+11:[ ]+c9[ ]+ret
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#pass
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@ -10,5 +10,9 @@ start
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jr start
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jr .L_next
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jr .L_xx
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label jp (hl)
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finish ret
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temp = 1234
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temp .defl 4321
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temp1 equ 4247
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.end
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@ -147,12 +147,12 @@ Disassembly of section .text:
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\s+124:\s+ed 8c\s+ind2
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\s+126:\s+ed 92\s+inimr
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\s+128:\s+ed 93\s+otimr
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\s+12a:\s+ed 94\s+oti2r
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\s+12a:\s+ed 94\s+ini2r
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\s+12c:\s+ed 9a\s+indmr
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\s+12e:\s+ed 9b\s+otdmr
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\s+130:\s+ed 9c\s+otd2r
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\s+132:\s+ed a4\s+ini2
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\s+134:\s+ed ac\s+ind2
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\s+130:\s+ed 9c\s+ind2r
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\s+132:\s+ed a4\s+outi2
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\s+134:\s+ed ac\s+outd2
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\s+136:\s+ed b4\s+oti2r
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\s+138:\s+ed bc\s+otd2r
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\s+13a:\s+ed c2\s+inirx
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34
gas/testsuite/gas/z80/ez80_unsup_regs.d
Normal file
34
gas/testsuite/gas/z80/ez80_unsup_regs.d
Normal file
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@ -0,0 +1,34 @@
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#name: eZ80 use unsupported registers as labels
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#as: -march=ez80 --defsym NO_REG_F= --defsym=EZ80=
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#objdump: -d
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#source: unsup_regs.s
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.*: .*
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Disassembly of section \.text:
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0+00 <_start>:
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[ ]+0:[ ]+dd 7d[ ]+ld a,ixl
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[ ]+2:[ ]+dd 67[ ]+ld ixh,a
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[ ]+4:[ ]+dd 44[ ]+ld b,ixh
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[ ]+6:[ ]+dd 68[ ]+ld ixl,b
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[ ]+8:[ ]+fd 4d[ ]+ld c,iyl
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[ ]+a:[ ]+fd 61[ ]+ld iyh,c
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[ ]+c:[ ]+fd 54[ ]+ld d,iyh
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[ ]+e:[ ]+fd 6a[ ]+ld iyl,d
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0+10 <f>:
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[ ]+10:[ ]+3e 10[ ]+ld a,0x10
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[ ]+12:[ ]+dd 29[ ]+add ix,ix
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[ ]+14:[ ]+dd 86 01[ ]+add a,\(ix\+1\)
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[ ]+17:[ ]+dd 21 34 12[ ]+ld ix,0x1234
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[ ]+1b:[ ]+fd 21 21 43[ ]+ld iy,0x4321
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[ ]+1f:[ ]+fd 22 34 12[ ]+ld \(0x1234\),iy
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[ ]+23:[ ]+fd 77 ff[ ]+ld \(iy\-1\),a
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[ ]+26:[ ]+ed 5f[ ]+ld a,r
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[ ]+28:[ ]+ed 4f[ ]+ld r,a
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[ ]+2a:[ ]+ed 57[ ]+ld a,i
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[ ]+2c:[ ]+ed 47[ ]+ld i,a
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[ ]+2e:[ ]+ed 6e[ ]+ld a,mb
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[ ]+30:[ ]+ed 6d[ ]+ld mb,a
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#pass
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@ -147,12 +147,12 @@ Disassembly of section .text:
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\s+124:\s+ed 8c\s+ind2
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\s+126:\s+ed 92\s+inimr
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\s+128:\s+ed 93\s+otimr
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\s+12a:\s+ed 94\s+oti2r
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\s+12a:\s+ed 94\s+ini2r
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\s+12c:\s+ed 9a\s+indmr
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\s+12e:\s+ed 9b\s+otdmr
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\s+130:\s+ed 9c\s+otd2r
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\s+132:\s+ed a4\s+ini2
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\s+134:\s+ed ac\s+ind2
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\s+130:\s+ed 9c\s+ind2r
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\s+132:\s+ed a4\s+outi2
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\s+134:\s+ed ac\s+outd2
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\s+136:\s+ed b4\s+oti2r
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\s+138:\s+ed bc\s+otd2r
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\s+13a:\s+ed c2\s+inirx
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45
gas/testsuite/gas/z80/gbz80_unsup_regs.d
Normal file
45
gas/testsuite/gas/z80/gbz80_unsup_regs.d
Normal file
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@ -0,0 +1,45 @@
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#name: GBZ80 use unsupported registers as labels
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#as: -march=gbz80 --defsym NO_XYHL= --defsym NO_REG_F= --defsym NO_REG_R= --defsym NO_REG_I= --defsym NO_INDEX=
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#objdump: -d
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#source: unsup_regs.s
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.*: .*
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Disassembly of section \.text:
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0+00 <_start>:
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[ ]+0:[ ]+3e 02[ ]+ld a,0x02
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0+02 <ixl>:
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[ ]+2:[ ]+06 04[ ]+ld b,0x04
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0+04 <ixh>:
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[ ]+4:[ ]+0e 06[ ]+ld c,0x06
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0+06 <iyl>:
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[ ]+6:[ ]+16 08[ ]+ld d,0x08
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0+08 <f>:
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[ ]+8:[ ]+3e 08[ ]+ld a,0x08
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0+0a <ix>:
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[ ]+a:[ ]+21 0a 00[ ]+ld hl,0x000a
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0+0d <iy>:
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[ ]+d:[ ]+01 0d 00[ ]+ld bc,0x000d
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[ ]+10:[ ]+fa 09 00[ ]+ld a,\(0x0009\)
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[ ]+13:[ ]+ea 0e 00[ ]+ld \(0x000e\),a
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0+16 <r>:
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[ ]+16:[ ]+3e 16[ ]+ld a,0x16
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[ ]+18:[ ]+ea 16 00[ ]+ld \(0x0016\),a
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0+1b <i>:
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[ ]+1b:[ ]+3e 1b[ ]+ld a,0x1b
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[ ]+1d:[ ]+ea 1b 00[ ]+ld \(0x001b\),a
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0+20 <mb>:
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[ ]+20:[ ]+21 20 00[ ]+ld hl,0x0020
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[ ]+23:[ ]+3e 20[ ]+ld a,0x20
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[ ]+25:[ ]+ea 20 00[ ]+ld \(0x0020\),a
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#pass
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35
gas/testsuite/gas/z80/r800_unsup_regs.d
Normal file
35
gas/testsuite/gas/z80/r800_unsup_regs.d
Normal file
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@ -0,0 +1,35 @@
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#name: R800 use unsupported registers as labels
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#as: -march=r800
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#objdump: -d
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#source: unsup_regs.s
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.*: .*
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Disassembly of section \.text:
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0+00 <_start>:
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[ ]+0:[ ]+dd 7d[ ]+ld a,ixl
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[ ]+2:[ ]+dd 67[ ]+ld ixh,a
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[ ]+4:[ ]+dd 44[ ]+ld b,ixh
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[ ]+6:[ ]+dd 68[ ]+ld ixl,b
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[ ]+8:[ ]+fd 4d[ ]+ld c,iyl
|
||||
[ ]+a:[ ]+fd 61[ ]+ld iyh,c
|
||||
[ ]+c:[ ]+fd 54[ ]+ld d,iyh
|
||||
[ ]+e:[ ]+fd 6a[ ]+ld iyl,d
|
||||
[ ]+10:[ ]+ed 70[ ]+in f,\(c\)
|
||||
[ ]+12:[ ]+dd 29[ ]+add ix,ix
|
||||
[ ]+14:[ ]+dd 86 01[ ]+add a,\(ix\+1\)
|
||||
[ ]+17:[ ]+dd 21 34 12 ld ix,0x1234
|
||||
[ ]+1b:[ ]+fd 21 21 43 ld iy,0x4321
|
||||
[ ]+1f:[ ]+fd 22 34 12 ld \(0x1234\),iy
|
||||
[ ]+23:[ ]+fd 77 ff[ ]+ld \(iy\-1\),a
|
||||
[ ]+26:[ ]+ed 5f[ ]+ld a,r
|
||||
[ ]+28:[ ]+ed 4f[ ]+ld r,a
|
||||
[ ]+2a:[ ]+ed 57[ ]+ld a,i
|
||||
[ ]+2c:[ ]+ed 47[ ]+ld i,a
|
||||
|
||||
0+2e <mb>:
|
||||
[ ]+2e:[ ]+21 2e 00[ ]+ld hl,0x002e
|
||||
[ ]+31:[ ]+3e 2e[ ]+ld a,0x2e
|
||||
[ ]+33:[ ]+32 2e 00[ ]+ld \(0x002e\),a
|
||||
#pass
|
||||
71
gas/testsuite/gas/z80/unsup_regs.s
Normal file
71
gas/testsuite/gas/z80/unsup_regs.s
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
.text
|
||||
.org 0
|
||||
_start:
|
||||
.ifdef NO_XYHL
|
||||
ld a,ixl
|
||||
ixl:
|
||||
ld b,ixh
|
||||
ixh:
|
||||
ld c,iyl
|
||||
iyl:
|
||||
ld d,iyh
|
||||
iyh:
|
||||
.else
|
||||
ld a,ixl
|
||||
ld ixh,a
|
||||
ld b,ixh
|
||||
ld ixl,b
|
||||
ld c,iyl
|
||||
ld iyh,c
|
||||
ld d,iyh
|
||||
ld iyl,d
|
||||
.endif
|
||||
|
||||
.ifdef NO_REG_F
|
||||
f: ld a,f
|
||||
.else
|
||||
in f,(c)
|
||||
.endif
|
||||
|
||||
.ifdef NO_INDEX
|
||||
ix: ld hl,ix
|
||||
iy: ld bc,iy
|
||||
ld a,(ix-1)
|
||||
ld (iy+1),a
|
||||
.else
|
||||
add ix,ix
|
||||
add a,(ix+1)
|
||||
ld ix,0x1234
|
||||
ld iy,0x4321
|
||||
ld (0x1234),iy
|
||||
ld (iy-1),a
|
||||
.endif
|
||||
|
||||
.ifdef NO_REG_R
|
||||
r: ld a,r
|
||||
ld (r),a
|
||||
.else
|
||||
ld a,r
|
||||
ld r,a
|
||||
.endif
|
||||
|
||||
.ifdef NO_REG_I
|
||||
i: ld a,i
|
||||
ld (i),a
|
||||
.else
|
||||
ld a,i
|
||||
ld i,a
|
||||
.endif
|
||||
|
||||
.ifndef EZ80
|
||||
mb: ld hl,mb
|
||||
ld a,mb
|
||||
ld (mb),a
|
||||
.else
|
||||
.assume ADL=1
|
||||
ld a,mb
|
||||
ld mb,a
|
||||
.assume ADL=0
|
||||
.endif
|
||||
|
||||
.END
|
||||
39
gas/testsuite/gas/z80/z180_unsup_regs.d
Normal file
39
gas/testsuite/gas/z80/z180_unsup_regs.d
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
#name: Z180 use unsupported registers as labels
|
||||
#as: -march=z180 --defsym NO_REG_F= --defsym NO_XYHL=
|
||||
#objdump: -d
|
||||
#source: unsup_regs.s
|
||||
|
||||
.*: .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+00 <_start>:
|
||||
[ ]+0:[ ]+3e 02[ ]+ld a,0x02
|
||||
|
||||
0+02 <ixl>:
|
||||
[ ]+2:[ ]+06 04[ ]+ld b,0x04
|
||||
|
||||
0+04 <ixh>:
|
||||
[ ]+4:[ ]+0e 06[ ]+ld c,0x06
|
||||
|
||||
0+06 <iyl>:
|
||||
[ ]+6:[ ]+16 08[ ]+ld d,0x08
|
||||
|
||||
0+08 <f>:
|
||||
[ ]+8:[ ]+3e 08[ ]+ld a,0x08
|
||||
[ ]+a:[ ]+dd 29[ ]+add ix,ix
|
||||
[ ]+c:[ ]+dd 86 01[ ]+add a,\(ix\+1\)
|
||||
[ ]+f:[ ]+dd 21 34 12 ld ix,0x1234
|
||||
[ ]+13:[ ]+fd 21 21 43 ld iy,0x4321
|
||||
[ ]+17:[ ]+fd 22 34 12 ld \(0x1234\),iy
|
||||
[ ]+1b:[ ]+fd 77 ff[ ]+ld \(iy\-1\),a
|
||||
[ ]+1e:[ ]+ed 5f[ ]+ld a,r
|
||||
[ ]+20:[ ]+ed 4f[ ]+ld r,a
|
||||
[ ]+22:[ ]+ed 57[ ]+ld a,i
|
||||
[ ]+24:[ ]+ed 47[ ]+ld i,a
|
||||
|
||||
0+26 <mb>:
|
||||
[ ]+26:[ ]+21 26 00[ ]+ld hl,0x0026
|
||||
[ ]+29:[ ]+3e 26[ ]+ld a,0x26
|
||||
[ ]+2b:[ ]+32 26 00[ ]+ld \(0x0026\),a
|
||||
#pass
|
||||
|
|
@ -17,93 +17,10 @@
|
|||
# run tests for target Z80.
|
||||
|
||||
if [istarget z80-*-*] then {
|
||||
# test redefinitions
|
||||
run_dump_test "redef"
|
||||
# test .set redefinitions
|
||||
run_dump_test "set"
|
||||
# test parsing of equ definitions
|
||||
run_dump_test "equ"
|
||||
# test parsing of " and '
|
||||
run_dump_test "quotes"
|
||||
# test data definition directives
|
||||
run_dump_test "data"
|
||||
# test suffixes
|
||||
run_dump_test "suffix"
|
||||
# test assembling and disassembling instructions involving offsets
|
||||
run_dump_test "offset"
|
||||
run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
|
||||
|
||||
gas_test_error "jr-forwf.s" "" "relative jump out of range (jr)"
|
||||
gas_test_error "jr-backf.s" "" "relative jump out of range (jr)"
|
||||
gas_test_error "djnz-backf.s" "" "relative jump out of range (djnz)"
|
||||
|
||||
# test assembling instruction with offset that is a label defined later
|
||||
run_dump_test "atend"
|
||||
# test for data transfer instructions
|
||||
run_dump_test "ld-group"
|
||||
# test for block instructions
|
||||
run_dump_test "block"
|
||||
# test for arithmetic and logic
|
||||
run_dump_test "arith"
|
||||
# test for rotate and shift
|
||||
run_dump_test "rotate"
|
||||
# test for bit manipulations
|
||||
run_dump_test "bit"
|
||||
# test for branch instructions
|
||||
run_dump_test "branch"
|
||||
# test for input and output instructions
|
||||
run_dump_test "inout"
|
||||
# test for strings
|
||||
run_dump_test "strings"
|
||||
# test for dollar labels
|
||||
run_dump_test "dollar"
|
||||
# test for relocations
|
||||
run_dump_test "z80_reloc"
|
||||
# test for absolutely all documented instructions of Z80
|
||||
run_dump_test "z80_doc"
|
||||
# test for undocumented instructions like RLC (IX+3),A
|
||||
run_dump_test "z80_op_ii_ld"
|
||||
# test for undocumented instructions SLI/SLL
|
||||
run_dump_test "z80_sli"
|
||||
# test for undocumented instruction IN F,(C)
|
||||
run_dump_test "z80_in_f_c"
|
||||
# test for undocumented instruction OUT (C),0
|
||||
run_dump_test "z80_out_c_0"
|
||||
# test for instructions with index register halves
|
||||
run_dump_test "z80_ii8"
|
||||
#test for other instructions
|
||||
run_dump_test "misc"
|
||||
gas_test_error "ill_op.s" "" "Illegal operand: ld hl,(sp+0)"
|
||||
# test for all Z80 documented instructions for R800
|
||||
run_dump_test "r800_z80_doc"
|
||||
# test for R800 instructions with index register halves
|
||||
run_dump_test "r800_ii8"
|
||||
# test for R800 extra instructions
|
||||
run_dump_test "r800_extra"
|
||||
#test for Z180 instructions
|
||||
run_dump_test "z180"
|
||||
#test for Z80 instructions while compiling for Z180
|
||||
run_dump_test "z180_z80_doc"
|
||||
#test for eZ80 instructions in Z80 mode
|
||||
run_dump_test "ez80_z80_all"
|
||||
#test for eZ80 instructions with sufficies in Z80 mode
|
||||
run_dump_test "ez80_z80_suf"
|
||||
#test for eZ80 instructions in ADL mode
|
||||
run_dump_test "ez80_adl_all"
|
||||
#test for eZ80 instructions with sufficies in ADL mode
|
||||
run_dump_test "ez80_adl_suf"
|
||||
#test for eZ80 opcode prefixes as multiple bytes before instruction
|
||||
run_dump_test "ez80_pref_dis"
|
||||
#test for GBZ80 instruction set
|
||||
run_dump_test "gbz80_all"
|
||||
#test for Z80N instruction set
|
||||
run_dump_test "z80n_all"
|
||||
#test for Z80N push nn relocation test
|
||||
run_dump_test "z80n_reloc"
|
||||
# test for SDCC compatibility mode
|
||||
run_dump_test "sdcc"
|
||||
# test for colonless labels
|
||||
run_dump_test "colonless"
|
||||
# test for FP math48
|
||||
run_dump_test "fp_math48"
|
||||
# test for FP zeda32
|
||||
run_dump_test "fp_zeda32"
|
||||
}
|
||||
|
|
|
|||
39
gas/testsuite/gas/z80/z80_strict_unsup_regs.d
Normal file
39
gas/testsuite/gas/z80/z80_strict_unsup_regs.d
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
#name: Z80 use unsupported registers as labels in strict mode
|
||||
#as: -march=z80-full --defsym NO_REG_F= --defsym NO_XYHL=
|
||||
#objdump: -d
|
||||
#source: unsup_regs.s
|
||||
|
||||
.*: .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+00 <_start>:
|
||||
[ ]+0:[ ]+3e 02[ ]+ld a,0x02
|
||||
|
||||
0+02 <ixl>:
|
||||
[ ]+2:[ ]+06 04[ ]+ld b,0x04
|
||||
|
||||
0+04 <ixh>:
|
||||
[ ]+4:[ ]+0e 06[ ]+ld c,0x06
|
||||
|
||||
0+06 <iyl>:
|
||||
[ ]+6:[ ]+16 08[ ]+ld d,0x08
|
||||
|
||||
0+08 <f>:
|
||||
[ ]+8:[ ]+3e 08[ ]+ld a,0x08
|
||||
[ ]+a:[ ]+dd 29[ ]+add ix,ix
|
||||
[ ]+c:[ ]+dd 86 01[ ]+add a,\(ix\+1\)
|
||||
[ ]+f:[ ]+dd 21 34 12 ld ix,0x1234
|
||||
[ ]+13:[ ]+fd 21 21 43 ld iy,0x4321
|
||||
[ ]+17:[ ]+fd 22 34 12 ld \(0x1234\),iy
|
||||
[ ]+1b:[ ]+fd 77 ff[ ]+ld \(iy\-1\),a
|
||||
[ ]+1e:[ ]+ed 5f[ ]+ld a,r
|
||||
[ ]+20:[ ]+ed 4f[ ]+ld r,a
|
||||
[ ]+22:[ ]+ed 57[ ]+ld a,i
|
||||
[ ]+24:[ ]+ed 47[ ]+ld i,a
|
||||
|
||||
0+26 <mb>:
|
||||
[ ]+26:[ ]+21 26 00[ ]+ld hl,0x0026
|
||||
[ ]+29:[ ]+3e 26[ ]+ld a,0x26
|
||||
[ ]+2b:[ ]+32 26 00[ ]+ld \(0x0026\),a
|
||||
#pass
|
||||
34
gas/testsuite/gas/z80/z80_unsup_regs.d
Normal file
34
gas/testsuite/gas/z80/z80_unsup_regs.d
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
#name: Z80 use unsupported registers as labels when no -march specified
|
||||
#objdump: -d
|
||||
#source: unsup_regs.s
|
||||
|
||||
.*: .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+00 <_start>:
|
||||
[ ]+0:[ ]+dd 7d[ ]+ld a,ixl
|
||||
[ ]+2:[ ]+dd 67[ ]+ld ixh,a
|
||||
[ ]+4:[ ]+dd 44[ ]+ld b,ixh
|
||||
[ ]+6:[ ]+dd 68[ ]+ld ixl,b
|
||||
[ ]+8:[ ]+fd 4d[ ]+ld c,iyl
|
||||
[ ]+a:[ ]+fd 61[ ]+ld iyh,c
|
||||
[ ]+c:[ ]+fd 54[ ]+ld d,iyh
|
||||
[ ]+e:[ ]+fd 6a[ ]+ld iyl,d
|
||||
[ ]+10:[ ]+ed 70[ ]+in f,\(c\)
|
||||
[ ]+12:[ ]+dd 29[ ]+add ix,ix
|
||||
[ ]+14:[ ]+dd 86 01[ ]+add a,\(ix\+1\)
|
||||
[ ]+17:[ ]+dd 21 34 12 ld ix,0x1234
|
||||
[ ]+1b:[ ]+fd 21 21 43 ld iy,0x4321
|
||||
[ ]+1f:[ ]+fd 22 34 12 ld \(0x1234\),iy
|
||||
[ ]+23:[ ]+fd 77 ff[ ]+ld \(iy\-1\),a
|
||||
[ ]+26:[ ]+ed 5f[ ]+ld a,r
|
||||
[ ]+28:[ ]+ed 4f[ ]+ld r,a
|
||||
[ ]+2a:[ ]+ed 57[ ]+ld a,i
|
||||
[ ]+2c:[ ]+ed 47[ ]+ld i,a
|
||||
|
||||
0+2e <mb>:
|
||||
[ ]+2e:[ ]+21 2e 00[ ]+ld hl,0x002e
|
||||
[ ]+31:[ ]+3e 2e[ ]+ld a,0x2e
|
||||
[ ]+33:[ ]+32 2e 00[ ]+ld \(0x002e\),a
|
||||
#pass
|
||||
34
gas/testsuite/gas/z80/z80n_unsup_regs.d
Normal file
34
gas/testsuite/gas/z80/z80n_unsup_regs.d
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
#name: Z80N use unsupported registers as labels
|
||||
#as: -march=z80n
|
||||
#objdump: -d
|
||||
#source: unsup_regs.s
|
||||
|
||||
.*: .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+00 <_start>:
|
||||
[ ]+0:[ ]+dd 7d[ ]+ld a,ixl
|
||||
[ ]+2:[ ]+dd 67[ ]+ld ixh,a
|
||||
[ ]+4:[ ]+dd 44[ ]+ld b,ixh
|
||||
[ ]+6:[ ]+dd 68[ ]+ld ixl,b
|
||||
[ ]+8:[ ]+fd 4d[ ]+ld c,iyl
|
||||
[ ]+a:[ ]+fd 61[ ]+ld iyh,c
|
||||
[ ]+c:[ ]+fd 54[ ]+ld d,iyh
|
||||
[ ]+e:[ ]+fd 6a[ ]+ld iyl,d
|
||||
[ ]+10:[ ]+ed 70[ ]+in f,\(c\)
|
||||
[ ]+12:[ ]+dd 29[ ]+add ix,ix
|
||||
[ ]+14:[ ]+dd 86 01[ ]+add a,\(ix\+1\)
|
||||
[ ]+17:[ ]+dd 21 34 12 ld ix,0x1234
|
||||
[ ]+1b:[ ]+fd 21 21 43 ld iy,0x4321
|
||||
[ ]+1f:[ ]+fd 22 34 12 ld \(0x1234\),iy
|
||||
[ ]+23:[ ]+fd 77 ff[ ]+ld \(iy\-1\),a
|
||||
[ ]+26:[ ]+ed 5f[ ]+ld a,r
|
||||
[ ]+28:[ ]+ed 4f[ ]+ld r,a
|
||||
[ ]+2a:[ ]+ed 57[ ]+ld a,i
|
||||
[ ]+2c:[ ]+ed 47[ ]+ld i,a
|
||||
|
||||
0+2e <mb>:
|
||||
[ ]+2e:[ ]+21 2e 00[ ]+ld hl,0x002e
|
||||
[ ]+31:[ ]+3e 2e[ ]+ld a,0x2e
|
||||
[ ]+33:[ ]+32 2e 00[ ]+ld \(0x002e\),a
|
||||
|
|
@ -400,24 +400,6 @@ cism (struct buffer *buf, disassemble_info * info, const char *txt ATTRIBUTE_UNU
|
|||
return buf->n_used;
|
||||
}
|
||||
|
||||
static int
|
||||
cis2 (struct buffer *buf, disassemble_info * info, const char *txt ATTRIBUTE_UNUSED)
|
||||
{
|
||||
static char * opar[] = { "in", "out" };
|
||||
char * op;
|
||||
char c;
|
||||
|
||||
c = buf->data[1];
|
||||
op = ((0x14 & c) == 0x14) ? "ot" : (opar[c & 1]);
|
||||
info->fprintf_func (info->stream,
|
||||
"%s%c2%s",
|
||||
op,
|
||||
(c & 0x08) ? 'd' : 'i',
|
||||
(c & 0x10) ? "r" : "");
|
||||
buf->n_used = 2;
|
||||
return buf->n_used;
|
||||
}
|
||||
|
||||
static int
|
||||
dump (struct buffer *buf, disassemble_info * info, const char *txt)
|
||||
{
|
||||
|
|
@ -504,21 +486,28 @@ struct tab_elt opc_ed[] =
|
|||
{ 0x7D, 0xFF, prt, "stmix", INSS_EZ80 },
|
||||
{ 0x7E, 0xFF, prt, "rsmix", INSS_EZ80 },
|
||||
{ 0x82, 0xE6, cism, "", INSS_Z180|INSS_EZ80 },
|
||||
{ 0x84, 0xC7, cis2, "", INSS_EZ80 },
|
||||
{ 0x84, 0xFF, prt, "ini2", INSS_EZ80 },
|
||||
{ 0x8A, 0xFF, prt_n_n, "push 0x%02x%%02x", INSS_Z80N },
|
||||
{ 0x8C, 0xFF, prt, "ind2", INSS_EZ80 },
|
||||
{ 0x90, 0xFF, prt, "outinb", INSS_Z80N },
|
||||
{ 0x91, 0xFF, prt_n_n, "nextreg 0x%02x,0x%%02x", INSS_Z80N },
|
||||
{ 0x92, 0xFF, prt_n, "nextreg 0x%02x,a", INSS_Z80N },
|
||||
{ 0x93, 0xFF, prt, "pixeldn", INSS_Z80N },
|
||||
{ 0x94, 0xFF, prt, "ini2r", INSS_EZ80 },
|
||||
{ 0x94, 0xFF, prt, "pixelad", INSS_Z80N },
|
||||
{ 0x95, 0xFF, prt, "setae", INSS_Z80N },
|
||||
{ 0x98, 0xFF, prt, "jp (c)", INSS_Z80N },
|
||||
{ 0x9c, 0xFF, prt, "ind2r", INSS_EZ80 },
|
||||
{ 0xA0, 0xE4, cis, "", INSS_ALL },
|
||||
{ 0xA4, 0xFF, prt, "outi2", INSS_EZ80 },
|
||||
{ 0xA4, 0xFF, prt, "ldix", INSS_Z80N },
|
||||
{ 0xAC, 0xFF, prt, "outd2", INSS_EZ80 },
|
||||
{ 0xAC, 0xFF, prt, "lddx", INSS_Z80N },
|
||||
{ 0xA5, 0xFF, prt, "ldws", INSS_Z80N },
|
||||
{ 0xB4, 0xFF, prt, "oti2r", INSS_EZ80 },
|
||||
{ 0xB4, 0xFF, prt, "ldirx", INSS_Z80N },
|
||||
{ 0xB7, 0xFF, prt, "ldpirx", INSS_Z80N },
|
||||
{ 0xBC, 0xFF, prt, "otd2r", INSS_EZ80 },
|
||||
{ 0xBC, 0xFF, prt, "lddrx", INSS_Z80N },
|
||||
{ 0xC2, 0xFF, prt, "inirx", INSS_EZ80 },
|
||||
{ 0xC3, 0xFF, prt, "otirx", INSS_EZ80 },
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue