Commit graph

4707 commits

Author SHA1 Message Date
Mike Frysinger
9a9db21d12 sim: m32r: invert sim_cpu storage
The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
63c5692305 sim: lm32: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
06f4b7b6d1 sim: iq2000: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
811727abbd sim: frv: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
8681713743 sim: cris: invert sim_cpu storage
The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
ef7878a286 sim: bpf: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
53891d9a7c sim: cgen: prep for inverting sim_cpu storage
Some common cgen code changes to allow cgen ports to invert their
sim_cpu storage one-by-one.
2022-12-21 00:00:01 -05:00
Mike Frysinger
5409cab77e sim: riscv: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
3d165c11f0 sim: pru: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
86ecb89bb7 sim: example-synacor: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
3fbdc6f908 sim: h8300: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
79d784aef9 sim: m68hc11: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
8e9408080b sim: mips: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
6d53d06992 sim: v850: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
620dd532fe sim: mcore: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6a08ae198b sim: aarch64: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
9dfc46c3d9 sim: microblaze: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
f246dc7285 sim: avr: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
778ef9bcbb sim: moxie: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
1c867d708c sim: msp430: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6780d3731e sim: ft32: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6adb107113 sim: bfin: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
ffeb72b44c sim: sim_cpu: invert sim_cpu storage
Currently all ports have to declare sim_cpu themselves in their
sim-main.h and then embed the common sim_cpu_base in it.  This
dynamic makes it impossible to share common object code among
multiple ports because the core data structure is always different.

Let's invert this relationship: common code declares sim_cpu, and
the port uses the new arch_data field for its per-cpu state.

This is the first in a series of changes: it adds a define to select
between the old & new layouts, then converts all the ports that don't
need custom state over to the new layout.  This includes mn10300 that,
while it defines custom fields in its cpu struct, never uses them.
2022-12-20 23:57:38 -05:00
Mike Frysinger
d026e67ed4 sim: move register headers into sim/ namespace [PR sim/29869]
These headers define the register numbers for each port to implement
the sim_fetch_register & sim_store_register interfaces.  While gdb
uses these, the APIs are part of the sim, not gdb.  Move the headers
out of the gdb/ include namespace and into sim/ instead.
2022-12-20 21:06:32 -05:00
Mike Frysinger
897903a210 sim: ppc: drop old dgen.c generator
The spreg.[ch] files live in the source tree now and are created
with the dgen.py script, so we don't need this old tool anymore.
2022-12-20 21:05:43 -05:00
Mike Frysinger
ee3314c436 sim: ppc: move spreg.[ch] files to the source tree
Simplify the build by moving the generation of these files from
build-time (via dgen.c that we have to compile & execute on the
build system) to maintainer/release mode (via spreg-gen.py that
we only ever execute when the spreg table actually changes).  It
speeds up the build process and makes it easier for us to reason
about & review changes to the code generator.

The tool is renamed from "dgen" because it's hardcoded to only
generated spreg files.  It isn't a generalized tool for creating
lookup tables.
2022-12-20 21:05:43 -05:00
Mike Frysinger
043f950abe sim: ppc: change spreg switch table generation to compile-time
Simplify the generator by always outputting the switch tables, and
leave the choice of whether to use them to the compiler via a -D
flag.
2022-12-19 20:32:34 -05:00
Mike Frysinger
09d236daec sim: dv-core: add hw_detach_address method [PR sim/25211]
The core device has an attach address method as the root of the tree
which calls out to the sim API.  But it doesn't have a corresponding
detach method which means we just crash if anything tries to detach
itself from the core.  In practice, the m68hc11 is the only model
that actually tries to detach itself on the fly, so no one noticed
earlier.

With this in place, we can delete the existing detach code from the
m68hc11 model since it defaults to "passthru" callback which will in
turn call the dv-core detach, and they have the same behavior -- call
the sim core API to detach from the address space.

Bug: https://sourceware.org/PR25211
2022-12-19 20:31:02 -05:00
Dimitar Dimitrov
7bee555bb7 sim: pru: Fix behaviour when loop count is zero
If the counter for LOOP instruction is provided by a register with
value zero, then the instruction must cause a PC jump directly to the
loop end.  But in that particular case simulator must not initialize
its internal loop variables, because loop body will not be executed.
Instead, simulator must obtain the loop's end address directly from
the LOOP instruction.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2022-11-12 15:10:07 +02:00
Mike Frysinger
36895e5335 sim: igen: cleanup archaic pointer-to-long printf casts
Use proper %p to printf a pointer instead of casting it to long and
using 0x%lx.  It's cleaner, more correct, and doesn't break on LLP64.
2022-11-11 22:08:14 +07:00
Mike Frysinger
897fc27b25 sim: v850: rename v850.dc to align with other ports
Other arches use the .dc extension for the instruction decode table.
2022-11-11 01:42:29 +07:00
Mike Frysinger
ef7c5fd15d sim: igen: fix hang when decoding boolean rule constants
The parser for boolean rules fails to skip over the , separator in
the options which makes it hang forever.  No dc files in the tree
use boolean rules atm which is why no one noticed.
2022-11-11 01:40:53 +07:00
Mike Frysinger
16cceb84be sim: igen: mark error func as noreturn since it exits 2022-11-11 01:40:35 +07:00
Mike Frysinger
c0c7e6ce2a sim: igen: mark output funcs with printf attribute
... and fix the legitimate bug that it catches.
2022-11-11 01:40:13 +07:00
Mike Frysinger
fa654e74f2 sim: igen: constify various func arguments 2022-11-11 01:39:49 +07:00
Mike Frysinger
689c2b4b65 sim: ppc: rename ppc-instructions to powerpc.igen
To make it clear this is an input to the igen tool, rename it with an
igen extension.  This matches the other files in the ppc dir (altivec
& e500 igen files), and the other igen ports (mips, mn10300, v850).
2022-11-11 01:38:42 +07:00
Mike Frysinger
64713044a4 sim: ppc: drop old makefile fragment
Support for these files was dropped almost 30 years ago, but the ppc
arch was missed.  Clean that up now too.
2022-11-10 14:45:47 +07:00
Mike Frysinger
7d95d825b3 sim: ppc: drop support for dgen -L option
Nothing passes this to dgen, and even if it did, nothing would happen
because the generated spreg.[ch] files don't include any references
back to the original data table.  So drop it to simplify.
2022-11-10 14:27:41 +07:00
Mike Frysinger
40466c48e8 sim: ppc: collapse is_readonly & length switch tables heavily
Since we know we'll return 0 by default, we don't have to output case
statements for readonly or length fields whose values are also zero.
This is the most common case by far and thus generates a much smaller
switch table in the end.
2022-11-10 14:27:41 +07:00
Mike Frysinger
1eff12f75a sim: ppc: collapse is_valid switch table more
Instead of writing:
  case 1:
    return 1;
  case 2:
    return 1;
  ...etc...

Output a single return so we get:
  case 1:
  case 2:
  case ...
    return 1;

This saves ~100 lines of code.  Hopefully the compiler was already
smart enough to optimize to the same code, but if not, this probably
helps there too :).
2022-11-10 14:27:40 +07:00
Mike Frysinger
99961e814f sim: ppc: pull default switch return out
This saves a single line for the same result.  By itself, it's not
interesting, but we can further optimize the generated output and
completely omit the switch table in some cases.  Which we'll do in
follow up commits.
2022-11-10 14:27:40 +07:00
Mike Frysinger
23af236b63 sim: ppc: constify spreg table
This internal table is only ever read, so constify it.
2022-11-10 14:27:40 +07:00
Mike Frysinger
3abad2f6a6 sim: igen: add missing newline to various error messages
The error() function expects a trailing newline in its message.
Most callers do this already, so adding it to the few that don't.
2022-11-10 00:29:27 +07:00
Mike Frysinger
959550953e sim: restore lstat & mkdir func checks
When merging ppc configure checks into the top-level, these 2 funcs
were accidentally dropped (probably due to incorrect resolution of
conflicts).  Restore them since the ppc code utilizes them both.
2022-11-10 00:19:45 +07:00
Mike Frysinger
31b40f11f1 sim: ppc: drop obsolete USE_WIN32API check
This controls only one thing: how to call mkdir().  The gnulib code
already has a mkdir module that provides this exact logic for us, so
punt the code entirely.
2022-11-10 00:13:36 +07:00
Mike Frysinger
c2264c8f78 sim: ppc: add missing parens with e500 macro
This macro expansion was missing a set of outer-most parenthesis which
some compilers would complain about depending on how the macro is used.
This is just standard good macro hygiene too.
2022-11-09 22:34:16 +07:00
Mike Frysinger
adcc07b94f sim: ppc: drop useless linking of helper tools
We've never run these helper programs directly.  The igen program
includes the relevant source files directly and runs the code that
way.  So stop wasting developer CPU time linking programs that are
never run.  We leave the rules in place for people who need to test
and debug the specific bits of code every now & then.
2022-11-09 22:34:16 +07:00
Mike Frysinger
2756004fe7 sim: mips: call Unpredictable instead of setting bogus values [PR sim/29276]
The intention of this code seems to be to indicate that this insn
should not be used and produces undefined behavior, so instead of
setting registers to bogus values, call Unpredictable.  This fixes
build warnings due to 32-bit/64-bit type conversions, and outputs
a log message for users at runtime instead of silent corruption.

Bug: https://sourceware.org/PR29276
2022-11-08 14:55:50 +07:00
Mike Frysinger
4faede6126 sim: riscv: add missing AC_MSG_RESULT call
Previous commit in here forgot to include this.
2022-11-07 23:44:36 +07:00
Mike Frysinger
871aa3b9ee sim: v850: drop subdir configure logic
We've been using this only to set the default word size to 32.  We
can easily move this into the makefile via a -D compiler flag and
clean up the build logic quite a bit.
2022-11-07 23:26:07 +07:00