Commit graph

4720 commits

Author SHA1 Message Date
Mike Frysinger
7dc3ab9125 sim: m32r: include sim-hw.h for sim_hw_parse 2022-12-22 19:13:40 -05:00
Mike Frysinger
2ac6aa431e sim: mips: merge mips64vr4300 with existing multi-run build
The existing mips64vr-* multi-run build already handles mips4300
targets, so reuse that for mips64vr43* targets too.  This moves
more logic from build-time to runtime so we can have a single
binary that supports many targets.
2022-12-22 19:04:23 -05:00
Mike Frysinger
2011a54779 sim: mips: match target on cpu settings
We don't need to enforce larger target settings when the only thing
the sim should care about is the CPU target.  So reduce most of the
target matches to only check the CPU.
2022-12-21 22:27:12 -05:00
Mike Frysinger
d455df988a sim: mips: move fpu bitsize defines to top-level configure
This drops support for the --enable-sim-float configure option,
but it's not clear anyone ever actually used that.  Eventually
we'll want this to be a runtime option anyways.
2022-12-21 22:27:12 -05:00
Mike Frysinger
19b11256a5 sim: mips: move bitsize defines to top-level configure
Since the msb value is always defined as the wordsize-1, stop
hardcoding that value directly, and use a CPP value instead.
2022-12-21 22:27:12 -05:00
Mike Frysinger
2d5700ad4e sim: mips: move subtarget defines to top-level configure
We want to kill off mips/configure entirely.  Move this small part
out now to get started.
2022-12-21 22:27:11 -05:00
Mike Frysinger
0fb6c560ff sim: mips: always resolve active bfd mach dynamically
Don't assume that the default bfd that we configured for is the one
that is always active when running a program.  We already have access
to the real runtime value, so use it directly.  This simplifies the
code quite a bit, and will make it easier to support multiple mach's
in a single binary.
2022-12-21 22:27:11 -05:00
Mike Frysinger
f4ac230605 sim: hw-config.h: move generation to top-level
In order to compile arch objects from the top-level, we need to
generate the hw-config.h header, so move that logic up to the top
level first.
2022-12-21 22:21:25 -05:00
Mike Frysinger
3d04211786 sim: build: hoist lists of hw devices up
We need these in the top-level to generate libsim.a, but also in the
subdirs to generate hw-config.h.  Move it to the local.mk, and pass
it down when running recursive make.  This avoids duplication, and
makes it available to both.  We can simplify this once we move the
various steps up to the top-level too.
2022-12-21 22:21:25 -05:00
Mike Frysinger
d47ea1b9c1 sim: build: hoist lists of common objects up
In order to create libsim.a in the common dir, we need the list of
objects for each target.  To avoid duplicating the list with the
recursive make in each port, pass it down as a variable.  This is
a temporary hack until the top-level creates libsim.a for ports.
2022-12-21 22:21:25 -05:00
Mike Frysinger
8df77a27a3 sim: fully merge sim_cpu_base into sim_cpu
Now that all ports have migrated to the new framework, drop support
for the old sim_cpu_base layout.  There's a lot of noise here, so
it's been split into a dedicated commit.
2022-12-21 00:00:19 -05:00
Mike Frysinger
4a21ad1e76 sim: enable common sim_cpu usage everywhere
All ports should be migrated now.  Drop the SIM_HAVE_COMMON_SIM_CPU
knob and require it be used everywhere now.
2022-12-21 00:00:18 -05:00
Mike Frysinger
4c3c31719b sim: or1k: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
9a9db21d12 sim: m32r: invert sim_cpu storage
The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
63c5692305 sim: lm32: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
06f4b7b6d1 sim: iq2000: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
811727abbd sim: frv: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
8681713743 sim: cris: invert sim_cpu storage
The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
ef7878a286 sim: bpf: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
53891d9a7c sim: cgen: prep for inverting sim_cpu storage
Some common cgen code changes to allow cgen ports to invert their
sim_cpu storage one-by-one.
2022-12-21 00:00:01 -05:00
Mike Frysinger
5409cab77e sim: riscv: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
3d165c11f0 sim: pru: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
86ecb89bb7 sim: example-synacor: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
3fbdc6f908 sim: h8300: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
79d784aef9 sim: m68hc11: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
8e9408080b sim: mips: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
6d53d06992 sim: v850: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
620dd532fe sim: mcore: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6a08ae198b sim: aarch64: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
9dfc46c3d9 sim: microblaze: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
f246dc7285 sim: avr: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
778ef9bcbb sim: moxie: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
1c867d708c sim: msp430: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6780d3731e sim: ft32: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6adb107113 sim: bfin: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
ffeb72b44c sim: sim_cpu: invert sim_cpu storage
Currently all ports have to declare sim_cpu themselves in their
sim-main.h and then embed the common sim_cpu_base in it.  This
dynamic makes it impossible to share common object code among
multiple ports because the core data structure is always different.

Let's invert this relationship: common code declares sim_cpu, and
the port uses the new arch_data field for its per-cpu state.

This is the first in a series of changes: it adds a define to select
between the old & new layouts, then converts all the ports that don't
need custom state over to the new layout.  This includes mn10300 that,
while it defines custom fields in its cpu struct, never uses them.
2022-12-20 23:57:38 -05:00
Mike Frysinger
d026e67ed4 sim: move register headers into sim/ namespace [PR sim/29869]
These headers define the register numbers for each port to implement
the sim_fetch_register & sim_store_register interfaces.  While gdb
uses these, the APIs are part of the sim, not gdb.  Move the headers
out of the gdb/ include namespace and into sim/ instead.
2022-12-20 21:06:32 -05:00
Mike Frysinger
897903a210 sim: ppc: drop old dgen.c generator
The spreg.[ch] files live in the source tree now and are created
with the dgen.py script, so we don't need this old tool anymore.
2022-12-20 21:05:43 -05:00
Mike Frysinger
ee3314c436 sim: ppc: move spreg.[ch] files to the source tree
Simplify the build by moving the generation of these files from
build-time (via dgen.c that we have to compile & execute on the
build system) to maintainer/release mode (via spreg-gen.py that
we only ever execute when the spreg table actually changes).  It
speeds up the build process and makes it easier for us to reason
about & review changes to the code generator.

The tool is renamed from "dgen" because it's hardcoded to only
generated spreg files.  It isn't a generalized tool for creating
lookup tables.
2022-12-20 21:05:43 -05:00
Mike Frysinger
043f950abe sim: ppc: change spreg switch table generation to compile-time
Simplify the generator by always outputting the switch tables, and
leave the choice of whether to use them to the compiler via a -D
flag.
2022-12-19 20:32:34 -05:00
Mike Frysinger
09d236daec sim: dv-core: add hw_detach_address method [PR sim/25211]
The core device has an attach address method as the root of the tree
which calls out to the sim API.  But it doesn't have a corresponding
detach method which means we just crash if anything tries to detach
itself from the core.  In practice, the m68hc11 is the only model
that actually tries to detach itself on the fly, so no one noticed
earlier.

With this in place, we can delete the existing detach code from the
m68hc11 model since it defaults to "passthru" callback which will in
turn call the dv-core detach, and they have the same behavior -- call
the sim core API to detach from the address space.

Bug: https://sourceware.org/PR25211
2022-12-19 20:31:02 -05:00
Dimitar Dimitrov
7bee555bb7 sim: pru: Fix behaviour when loop count is zero
If the counter for LOOP instruction is provided by a register with
value zero, then the instruction must cause a PC jump directly to the
loop end.  But in that particular case simulator must not initialize
its internal loop variables, because loop body will not be executed.
Instead, simulator must obtain the loop's end address directly from
the LOOP instruction.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2022-11-12 15:10:07 +02:00
Mike Frysinger
36895e5335 sim: igen: cleanup archaic pointer-to-long printf casts
Use proper %p to printf a pointer instead of casting it to long and
using 0x%lx.  It's cleaner, more correct, and doesn't break on LLP64.
2022-11-11 22:08:14 +07:00
Mike Frysinger
897fc27b25 sim: v850: rename v850.dc to align with other ports
Other arches use the .dc extension for the instruction decode table.
2022-11-11 01:42:29 +07:00
Mike Frysinger
ef7c5fd15d sim: igen: fix hang when decoding boolean rule constants
The parser for boolean rules fails to skip over the , separator in
the options which makes it hang forever.  No dc files in the tree
use boolean rules atm which is why no one noticed.
2022-11-11 01:40:53 +07:00
Mike Frysinger
16cceb84be sim: igen: mark error func as noreturn since it exits 2022-11-11 01:40:35 +07:00
Mike Frysinger
c0c7e6ce2a sim: igen: mark output funcs with printf attribute
... and fix the legitimate bug that it catches.
2022-11-11 01:40:13 +07:00
Mike Frysinger
fa654e74f2 sim: igen: constify various func arguments 2022-11-11 01:39:49 +07:00
Mike Frysinger
689c2b4b65 sim: ppc: rename ppc-instructions to powerpc.igen
To make it clear this is an input to the igen tool, rename it with an
igen extension.  This matches the other files in the ppc dir (altivec
& e500 igen files), and the other igen ports (mips, mn10300, v850).
2022-11-11 01:38:42 +07:00
Mike Frysinger
64713044a4 sim: ppc: drop old makefile fragment
Support for these files was dropped almost 30 years ago, but the ppc
arch was missed.  Clean that up now too.
2022-11-10 14:45:47 +07:00