bfin-dis.c:160 shift exponent 32 is too large for 32-bit type 'long unsigned int'
bpf-ibld.c:196 left shift of 1 by 31 places cannot be represented in type 'long int'
bpf-ibld.c:196 negation of -2147483648 cannot be represented in type 'long int'; cast to an unsigned type to negate this
itself
bpf-ibld.c:197 left shift of 1 by 31 places cannot be represented in type 'long int'
bpf-ibld.c:197 signed integer overflow: -2147483648 - 1 cannot be represented in type 'long int'
bpf-ibld.c:501 left shift of 1 by 31 places cannot be represented in type 'long int'
* cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
* bpf-ibld.c: Regenerate.
* epiphany-ibld.c: Regenerate.
* fr30-ibld.c: Regenerate.
* frv-ibld.c: Regenerate.
* ip2k-ibld.c: Regenerate.
* iq2000-ibld.c: Regenerate.
* lm32-ibld.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32r-ibld.c: Regenerate.
* mep-ibld.c: Regenerate.
* mt-ibld.c: Regenerate.
* or1k-ibld.c: Regenerate.
* xc16x-ibld.c: Regenerate.
* xstormy16-ibld.c: Regenerate.
Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is
enabled by ck803r3, and it's still a part of enhance DSP instruction
set.
gas/
* config/tc-csky.c (csky_cpus): Add ck803r3.
(CSKY_ISA_803R3): Define.
(CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
include/
* opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
opcodes/
* csky-opc.h (csky_v2_opcodes): Move divul and divsl
to CSKYV2_ISA_3E3R3 instruction set.
cpu/
* mep-core.cpu (f-8s8a2, f-12s4a2, f-17s16a2): Multiply signed
value by two rather than shifting left.
(f-24s5a2n): Similarly multiply signed f-24s5a2n-hi to extract.
opcodes/
* mep-ibld.c: Regenerate.
When looking at the UB errors, I noticed that cbitb_test.d disassembly
wasn't reproducing the input assembly. That turned out to be an error
in make_argument case arg_cr. This fixes that and makes some general
tidies.
opcodes/
* cr16-dis.c: Formatting.
(parameter): Delete struct typedef. Use dwordU instead
throughout file.
(make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
and tbitb.
(make_argument <arg_cr>): Extract 20-bit field not 16-bit.
gas/
* testsuite/gas/cr16/cbitb_test.d: Update expected output.
* testsuite/gas/cr16/cbitw_test.d: Likewise.
* testsuite/gas/cr16/sbitb_test.d: Likewise.
* testsuite/gas/cr16/sbitw_test.d: Likewise.
* testsuite/gas/cr16/storb_test.d: Likewise.
* testsuite/gas/cr16/storw_test.d: Likewise.
* testsuite/gas/cr16/tbitb_test.d: Likewise.
* testsuite/gas/cr16/tbitw_test.d: Likewise.
This patch adds support for xBPF, another ISA targetting the BPF
virtual architecture. For now, the primary difference between eBPF
and xBPF is that xBPF supports indirect calls through the
'call %reg' form of the call instruction.
bfd/
* archures.c (bfd_mach_xbpf): Define.
* bfd-in2.h: Regenerate.
* cpu-bpf.c (bfd_xbpf_arch) New.
(bfd_bpf_arch) Update next in list field to point to xbpf arch.
cpu/
* bpf.cpu (arch bpf): Add xbpf mach and isas.
(define-xbpf-isa) New pmacro.
(all-isas) Add xbpfle,xbpfbe.
(endian-isas): New pmacro.
(mach xbpf): New.
(model xbpf-def): Likewise.
(h-gpr): Add xbpf mach.
(f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
(f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
(define-alu-insn-un): Use new endian-isas pmacro.
(define-alu-insn-bin, define-alu-insn-mov): Likewise.
(define-endian-insn, define-lddw): Likewise.
(dlind, dxli, dxsi, dsti): Likewise.
(define-cond-jump-insn, define-call-insn): Likewise.
(define-atomic-insns): Likewise.
gas/
* config/tc-bpf.c: Add option -mxbpf to select xbpf isa.
* testsuite/gas/bpf/indcall-1.d: New file.
* testsuite/gas/bpf/indcall-1.s: Likewise.
* testsuite/gas/bpf/indcall-bad-1.l: Likewise.
* testsuite/gas/bpf/indcall-bad-1.s: Likewise.
* testsuite/gas/bpf/bpf.exp: Run new tests.
opcodes/
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
* disassemble.c (disassemble_init_for_target): Set bits for xBPF
ISA when appropriate.
bfd * elfnn-aarch64.c (_bfd_aarch64_erratum_835769_scan): Only sort
the data map if there are entries in it.
(_bfd_aarch64_erratum_843419_scan): Likewise.
opcodes * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
symbols.
gas/
* config/tc-csky.c (csky_insn_info): Add member last_isize.
(md_assemble): Assign value to csky_insn.last_isize.
* testsuite/gas/csky/enhance_dsp.d: Test bloop's two operands form.
* testsuite/gas/csky/enhance_dsp.s: Likewise.
opcodes/
* csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
These shouldn't be optional. The record form of vector instructions
set CR6, giving an expectation that omitting BF should be the same as
specifying CR6.
opcodes/
* ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
vcmpuq and xvtlsbb.
gas/
* testsuite/gas/ppc/int128.s: Correct vcmpuq.
* testsuite/gas/ppc/int128.d: Update.
* testsuite/gas/ppc/xvtlsbb.d: Update.
This patch adds support for the system registers introduced in the
Armv8-A MPAM extension.
See https://developer.arm.com/documentation/ddi0598/latest for the
Arm ARM supplement documenting this extension.
gas/ChangeLog:
* testsuite/gas/aarch64/mpam-bad.d: New test.
* testsuite/gas/aarch64/mpam-bad.l: Error output.
* testsuite/gas/aarch64/mpam-bad.s: Input.
* testsuite/gas/aarch64/mpam.d: New test.
* testsuite/gas/aarch64/mpam.s: Input.
opcodes/ChangeLog:
* aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
Problem found by Tadashi G. Takaoka.
2020-08-04 Christian Groessler <chris@groessler.org>
Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
* z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
opcodes (special "out" to absolute address).
* z8k-opc.h: Regenerate.
2020-08-04 Christian Groessler <chris@groessler.org>
* gas/testsuite/gas/z8k/inout.d: Adapt to correct encoding of
"sout/soutb #imm,reg"
In s390-mkopc.c, the function insertExpandedMnemonic() searches for the
first occurrence of '*' or '$' in the given mnemonic, and, if a match is
found, chooses an extension table using a switch() on that character. The
switch statement contains a default case that prints an error message and
does not set the extension table. Although this case cannot occur, some
GCC versions obviously conclude that the extension table might have been
left uninitialized after the switch statement and consequently emit
maybe-uninitialized warnings for the variables 'ext_table' and
'ext_table_length'.
Circumvent the warning by handling the unreachable default case with
abort().
opcodes/
* s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
default case with abort() instead of printing an error message and
continuing, to avoid a maybe-uninitialized warning.
This reverts commit 04c662e2b6.
In my underlying suggestion I neglected the fact that in those
cases (,%eiz,1) is the only visible indication that 32-bit
addressing is in effect.
Change
67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef(,%eiz,1),%rbx
to
67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef,%rbx
in AT&T syntax and
67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR [eiz*1+0x89abcdef]
to
67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR ds:0x89abcdef
in Intel syntax.
gas/
PR gas/26237
* testsuite/gas/i386/evex-no-scale-64.d: Updated.
* testsuite/gas/i386/addr32.d: Likewise.
* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/x86-64-addr32.d: Likewise.
opcodes/
PR gas/26237
* i386-dis.c (OP_E_memory): Don't display eiz with no scale
without base nor index registers.
Irrespective of their encoding the resulting output should look the
same. Therefore wire the handling of PUSH/POP with GPR operands
encoded in the main opcode byte to the same logic used for other
operands. This frees up yet another macro character.
"Unambiguous" is is in particular taking as reference the assembler,
which also accepts certain insns - despite them allowing for varying
operand size, and hence in principle being ambiguous - without any
suffix. For example, from the very beginning of the life of x86-64 I had
trouble understanding why a plain and simple RET had to be printed as
RETQ. In case someone really used the 16-bit form, RETW disambiguates
the two quite fine.
Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to
64 bits, change disassembler to zero-extend the lower 32 bits displacement
to 64 bits when there is no base nor index registers.
gas/
PR gas/26237
* testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around
address.
* testsuite/gas/i386/x86-64-addr32.s: Likewise.
* testsuite/gas/i386/addr32.d: Updated.
* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/x86-64-addr32.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise.
opcodes/
PR gas/26237
* i386-dis.c (OP_E_memory): Without base nor index registers,
32-bit displacement to 64 bits.
ARC can use odd-even double register pairs in some selected
instructions. Although the GNU assembler doesn't allow even-odd
registers to be used, there may be cases when the disassembler is
presented with such situation. This patch add a test and detects such
cases.
opcodes/
2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
* arc-dis.c (print_insn_arc): Detect and emit a warning when a
faulty double register pair is detected.
binutils/
2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
* testsuite/binutils-all/arc/double_regs.s: New test.
* testsuite/binutils-all/arc/objdump.exp: Add the above test.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
%db<n> is an AT&T invention; the Intel documentation and MASM have only
ever specified DRn (in line with CRn and TRn). (In principle gas also
shouldn't accept the names in Intel mode, but at least for now I've kept
things as they are. Perhaps as a first step this should just be warned
about.)
Rm (and hence OP_R()) can be dropped by making 'Z' force modrm.mod to 3
(for OP_E()) instead of ignoring it. While at it move 'Z' handling to
its designated place (after 'Y'; 'W' handling will be moved by a later
change).
Moves to/from TRn are illegal in 64-bit mode and thus get converted to
honor this at the same time (also getting them in line with moves
to/from CRn/DRn ModRM.mod handling wise). This then also frees up the L
macro.
Rdq, Rd, and MaskR can be replaced by Edq, Ed / Rm, and MaskE
respectively, as OP_R() doesn't enforce ModRM.mod == 3, and hence where
MOD matters but hasn't been decoded yet it needs to be anyway. (The case
of converting to Rm is temporary until a subsequent change.)
In this case there's no need to go through prefix_table[] at all - the
.prefix_requirement == PREFIX_OPCODE machinery takes care of this case
already.
A couple of further adjustments are needed though:
- Gv / Ev and alike then can't be used (needs to be Gdq / Edq instead),
- dq_mode and friends shouldn't lead to PREFIX_DATA getting set in
used_prefixes.
The only valid (embedded or explicit) prefix being the data size one
(which is a fairly common pattern), avoid going through prefix_table[].
Instead extend the "required prefix" logic to also handle PREFIX_DATA
alone in a table entry, now used to identify this case. This requires
moving the (adjusted) ->prefix_requirement logic ahead of the printing
of stray prefixes, as the latter needs to observe the new setting of
PREFIX_DATA in used_prefixes.
Also add PREFIX_OPCODE on related entries when previously there was
mistakenly no decode step through prefix_table[].
It was quite odd for the prior operand handling to have to clear this
flag for the actual operand handling to print nothing. Have the actual
operand handling determine whether the operand is actually present.
With this {d,q}_scalar_swap_mode become unused and hence also get dropped.
These are only used when VEX.L or EVEX.L'L have already been decoded,
and hence the "normal" length dependent name determination is quite
fine. Adjust a few enumerators to make clear that vex_len_table[] has
been consulted; be consistent and do so for all *f128 and *i128 insns
in one go.
Fold redundant case blocks and move the extra adjustments logic into
the single case block that actually needs it - there's no need to go
through the extra logic for all the other cases. Also utilize there that
vex.b cannot be set at this point, due to earlier logic. Reduce the
comment there, which was partly stale anyway.
