The previous change
"x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit mode"
to ignore segment override prefixes in 64-bit mode lead to dumping
branch hints as excessive prefixes:
ffffffff8109d5a0 <vmx_get_rflags>:
...
ffffffff8109d601: 3e 77 0a ds ja,pt ffffffff8109d60e <vmx_get_rflags+0x6e>
^^^^^
In this particular case, those prefixes are not excessive but are used
to provide branch hints - taken/not-taken - to the CPU.
Assign active_seg_prefix in that particular case to consume them.
gas/
2002-11-29 Borislav Petkov <bp@suse.de>
* testsuite/gas/i386/branch.d: Add new branch insns test.
* testsuite/gas/i386/branch.s: Likewise.
* testsuite/gas/i386/i386.exp: Insert the new branch test.
* testsuite/gas/i386/x86-64-branch.d: Test for branch hints insns.
* testsuite/gas/i386/x86-64-branch.s: Likewise.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
opcodes/
2020-11-28 Borislav Petkov <bp@suse.de>
* i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns
to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.
Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A.
Please note that FLAGM stays a Armv8.4-A feature but now can be
assigned to other architectures or CPUs.
New -march option +flagm is added to enable independently this
feature.
include * opcode/pru.h: Add LMBD (left-most bit detect) opcode index
opcodes * pru-opc.c: Add opcode description for LMBD (left-most bit detect)
gas * testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit detect)
* testsuite/gas/pru/misc.d: Add tests for lmbd (left-most bit
This patch:
+ Adds new ACCDATA_EL1 (Accelerator Data) system register, see [0].
+ Adds LS64 instruction tests.
+ Update LS64 feature test with new register.
+ Fix comment for AARCH64_OPND_Rt_LS64.
[0] https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/accdata_el1
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
Atomic 64-byte load/store instructions limit Rt register number to
values matching below condition (register <Xt> number must be even
and <= 22):
if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;
This patch adds check if Rt fulfills above requirement.
For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
Extract PAC (Pointer Authentication) feature from Armv8.3-A.
Please note that PAC stays a Armv8.3-A feature but now can be
assigned to other architectures or CPUs.
This patch:
+ updates RAS feature system registers with new RAS 1.1 regs.
+ extends RAS/RAS 1.1 support for all architecture levels of Armv8-A.
Please note that early Armv8-A architectures do not officially support RAS
extension.
Rationale of the patch:
To ease development so that user-friendly RAS system registers operands can be
used. Certain use cases require developers to enable only more generic
architecture (e.g. -march=armv8-a) during system development. Users must use
RAS extension registers bearing in mind that system they use must support it.
The RAS (Reliability, Availability, Serviceability) extension is a
system-level extension that defines a number of system registers.
RAS 1.1 (FEAT_RASv1p1) introduces five new system registers:
ERXPFGCTL_EL1, ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and
ERXPFGF_EL1.
For details see [0].
[0] https://developer.arm.com/docs/ddi0595/i/
Armv8.7 architecture introduces the "accelerator extension", aka
load/store of 64 bytes. New atomic load/store instructions are: LD64B,
ST64B, ST64BV and ST64BV0.
This patch adds:
+ New feature +ls64 to -march command line.
+ New atomic load/store instructions associated with above feature.
For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/
* config/tc-csky.c (get_operand_value): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* testsuite/gas/csky/csky_vdsp.d : Fix the disassembling
for vector register.
opcodes/
* csky-dis.c (csky_output_operand): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
(OPRND_TYPE_IMM5b_VSH): New enum.
(csky_v2_opcodes): Fix and add some instructions for VDSPV1.
Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb
Remove the duplicated entry in opcodes/po/es.po:
binutils-gdb/opcodes/po/es.po:749: duplicate message definition...
binutils-gdb/opcodes/po/es.po:742: ...this is the location of the first definition
* po/es.po: Remove the duplicated entry.
bfd * po/es.po: Fix printf format
binutils * windmc.c: Fix printf format
gas * config/tc-arc.c: Fix printf format
opcodes * po/es.po: Fix printf format
sim * arm/armos.c: Fix printf format
* ppc/emul_netbsd.c: Fix printf format
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
Rename VexOpcode to OpcodePrefix so that OpcodePrefix can be used for
regular encoding prefix.
gas/
* config/tc-i386.c (build_vex_prefix): Replace vexopcode with
opcodeprefix.
(build_evex_prefix): Likewise.
(is_any_vex_encoding): Don't check vexopcode.
(output_insn): Handle opcodeprefix.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VexOpcode with
OpcodePrefix.
* i386-opc.h (VexOpcode): Renamed to ...
(OpcodePrefix): This.
(PREFIX_NONE): New.
(PREFIX_0X66): Likewise.
(PREFIX_0XF2): Likewise.
(PREFIX_0XF3): Likewise.
* i386-opc.tbl (Prefix_0X66): New.
(Prefix_0XF2): Likewise.
(Prefix_0XF3): Likewise.
Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
* i386-tbl.h: Regenerated.
In 64bit, assembler generates a warning for "sysret":
$ echo sysret | as --64 -o x.o -
{standard input}: Assembler messages:
{standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret'
Always display suffix for %LQ in 64bit to display "sysretl".
gas/
PR binutils/26704
* testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of
sysret.
* testsuite/gas/i386/noreg64.d: Likewise.
* testsuite/gas/i386/x86-64-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
opcodes/
PR binutils/26704
* i386-dis.c (putop): Always display suffix for %LQ in 64bit.
The MODRM byte can be checked to display the instruction name only if the
MODRM byte needed. Clear modrm if the MODRM byte isn't needed so that
modrm field checks in putop like, modrm.mod == N with N != 0, can be done
without checking need_modrm.
gas/
PR binutils/26705
* testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before
sysretq.
* testsuite/gas/i386/x86-64-suffix-intel.d: Updated.
* testsuite/gas/i386/x86-64-suffix.d: Likewise.
opcodes/
PR binutils/26705
* i386-dis.c (print_insn): Clear modrm if not needed.
(putop): Check need_modrm for modrm.mod != 3. Don't check
need_modrm for modrm.mod == 3.
gas * testsuite/gas/aarch64/ete.d: New test.
* testsuite/gas/aarch64/ete.s: New test.
opcodes * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
gas * testsuite/gas/aarch64/trbe-invalid.d: New test.
* testsuite/gas/aarch64/trbe-invalid.l: New test.
* testsuite/gas/aarch64/trbe-invalid.s: New test.
* testsuite/gas/aarch64/trbe.d: New test.
* testsuite/gas/aarch64/trbe.s: New test.
opcodes * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
There are 11 MOD_VEX_0F38* inserted in MOD_0F38* group,
which should be placed in MOD_VEX_0F38* group.
opcode/
PR 26654
*i386-dis.c (enum): Put MOD_VEX_0F38* together.
This commit:
commit afdcafe891
Date: Thu Sep 17 14:30:28 2020 +0800
CSKY: Add objdump option -M abi-names.
cases the build of GDB (configured with --enabled-targets=all) to fail
with this error:
libtool: compile: gcc -DHAVE_CONFIG_H -I. -I../../src/opcodes -I. -I../../src/opcodes -I../bfd -I../../src/opcodes/../include -I../../src/opcodes/../bfd -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Wstack-usage=262144 -Werror -O0 -g3 -D_GLIBCXX_DEBUG=1 -MT csky-dis.lo -MD -MP -MF .deps/csky-dis.Tpo -c ../../src/opcodes/csky-dis.c -o csky-dis.o
../../src/opcodes/csky-dis.c: In function 'csky_output_operand':
../../src/opcodes/csky-dis.c:849:7: error: this 'if' clause does not guard... [-Werror=misleading-indentation]
849 | if (IS_CSKY_V1 (mach_flag))
| ^~
../../src/opcodes/csky-dis.c:851:2: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
851 | strcat (str, buf);
| ^~~~~~
this commit adds { ... } around the if body to resolve this issue.
opcodes/ChangeLog:
* csky-dis.c (csky_output_operand): Enclose body of if in curly
braces.
Add option parser for disassembler, and refine the codes of
parse register operand and disassemble register operand.
While strengthen the operands legality check of some instructions.
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (parse_type_ctrlreg): Use function
csky_get_control_regno to operand.
(csky_get_reg_val): Likewise.
(is_reg_sp_with_bracket): Use function csky_get_reg_val
to parse operand.
(is_reg_sp): Refine.
(is_oimm_within_range): Fix, report error when operand
is not constant.
(parse_type_cpreg): Refine.
(parse_type_cpcreg): Refine.
(get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS.
(md_assemble): Fix no error reporting somtimes when
operands number are not fit.
(csky_addc64): Refine.
(csky_subc64): Refine.
(csky_or64): Refine.
(v1_work_fpu_fo): Refine.
(v1_work_fpu_read): Refine.
(v1_work_fpu_writed): Refine.
(v1_work_fpu_readd): Refine.
(v2_work_addc): New function, strengthen the operands legality
check of addc.
* gas/testsuite/gas/csky/all.d : Use register number format when
disassemble register name by default.
* gas/testsuite/gas/csky/cskyv2_all.d : Likewise.
* gas/testsuite/gas/csky/trust.d: Likewise.
* gas/testsuite/gas/csky/cskyv2_ck860.d : Fix.
* gas/testsuite/gas/csky/trust.s : Fix.
opcodes/
* csky-dis.c (using_abi): New.
(parse_csky_dis_options): New function.
(get_gr_name): New function.
(get_cr_name): New function.
(csky_output_operand): Use get_gr_name and get_cr_name to
disassemble and add handle of OPRND_TYPE_IMM5b_LS.
(print_insn_csky): Parse disassembler options.
* opcodes/csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
(GENARAL_REG_BANK): Define.
(REG_SUPPORT_ALL): Define.
(REG_SUPPORT_ALL): New.
(ASH): Define.
(REG_SUPPORT_A): Define.
(REG_SUPPORT_B): Define.
(REG_SUPPORT_C): Define.
(REG_SUPPORT_D): Define.
(REG_SUPPORT_E): Define.
(csky_abiv1_general_regs): New.
(csky_abiv1_control_regs): New.
(csky_abiv2_general_regs): New.
(csky_abiv2_control_regs): New.
(get_register_name): New function.
(get_register_number): New function.
(csky_get_general_reg_name): New function.
(csky_get_general_regno): New function.
(csky_get_control_reg_name): New function.
(csky_get_control_regno): New function.
(csky_v2_opcodes): Prefer two oprerans format for bclri and
bseti, strengthen the operands legality check of addc, zext
and sext.
Add gas and opcodes support for two xBPF-exclusive ALU operations:
SDIV (signed division) and SMOD (signed modulo), and add tests for
them in gas.
cpu/
* bpf.cpu (insn-op-code-alu): Add SDIV and SMOD.
(define-alu-insn-bin, daib): Take ISAs as an argument.
(define-alu-instructions): Update calls to daib pmacro with
ISAs; add sdiv and smod.
gas/
* testsuite/gas/bpf/alu-xbpf.d: New file.
* testsuite/gas/bpf/alu-xbpf.s: Likewise.
* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
* testuiste/gas/bpf/bpf.exp: Run new tests.
opcodes/
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
The disassembler function should return a valid disassembler function
even when there is no BFD present. This is implied (I believe) by the
comment in dis-asm.h which says the BFD may be NULL. Further, it
makes sense when considering that the disassembler is used in GDB, and
GDB may connect to a target and perform debugging even without a BFD
being supplied.
This commit makes the csky_get_disassembler function return the
default disassembler configuration when no bfd is supplied, this is
the same default configuration as is used when a BFD is supplied, but
the BFD has no attributes section.
Before the change configuring GDB with --enable-targets=all and
running the tests gdb.base/all-architectures-2.exp results in many
errors, but after this change there are no failures.
opcodes/ChangeLog:
* csky-dis.c (csky_get_disassembler): Don't return NULL when there
is no BFD.
* ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
for hidden, local, no-type symbols.
(disassemble_init_powerpc): Point the symbol_is_valid field in the
info structure at the new function.
incldue * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Use a long long type for
this value.
opcodes * csky-dis.c (csky_output_operand): Coerce the immediate values to
long before printing.
This patch adds support for the system registers introduced in Armv8-R
AArch64.
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to
validation function.
(parse_sys_ins_reg): Likewise.
(print_operands): Pass CPU features to aarch64_print_operand().
* testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test.
* testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output.
* testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input.
* testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test.
* testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output.
* testsuite/gas/aarch64/v8-r-sysregs.d: New test.
* testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests.
include/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (aarch64_sys_ins_reg_supported_p): Also take
system register name in order to simplify validation for v8-R.
(aarch64_print_operand): Also take CPU feature set, as disassembly for
system registers now depends on arch variant.
opcodes/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* aarch64-dis.c (print_operands): Pass CPU features to
aarch64_print_operand().
* aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
preferred disassembly of system registers.
(SR_RNG): Refactor to use new SR_FEAT2 macro.
(SR_FEAT2): New.
(SR_V8_1_A): New.
(SR_V8_4_A): New.
(SR_V8_A): New.
(SR_V8_R): New.
(SR_EXPAND_ELx): New.
(SR_EXPAND_EL12): New.
(aarch64_sys_regs): Specify which registers are only on
A-profile, add R-profile system registers.
(ENC_BARLAR): New.
(PRBARn_ELx): New.
(PRLARn_ELx): New.
(aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
Armv8-R AArch64.
This patch adds the basic infrastructure needed to support Armv8-R in
AArch64 binutils: new command-line flags, new feature bits, a new BFD
architecture, and support for differentiating between architecture
variants in the disassembler.
The new command-line options added by this patch are -march=armv8-r in
GAS and -m aarch64:armv8-r in objdump.
The disassembler support is necessary since Armv8-R AArch64 introduces a
system register (VSCTLR_EL2) which shares an encoding with a different
system register (TTBR0_EL2) in Armv8-A. This also allows us to use the
correct preferred disassembly for the new DFB alias introduced in
Armv8-R.
bfd/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* archures.c (bfd_mach_aarch64_8R): New.
* bfd-in2.h: Regenerate.
* cpu-aarch64.c (bfd_aarch64_arch_v8_r): New.
(bfd_aarch64_arch_ilp32): Update tail pointer.
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (aarch64_archs): Add armv8-r.
* doc/c-aarch64.texi: Document -march=armv8-r.
include/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_A): New.
(AARCH64_FEATURE_V8_R): New.
(AARCH64_ARCH_V8): Include new A-profile feature bit.
(AARCH64_ARCH_V8_R): New.
opcodes/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* aarch64-dis.c (arch_variant): New.
(determine_disassembling_preference): Disassemble according to
arch variant.
(select_aarch64_variant): New.
(print_insn_aarch64): Set feature set.
i386-dis.c:12207 left shift of 128 by 24 places cannot be represented in type 'long int'
i386-dis.c:12220 left shift of 128 by 24 places cannot be represented in type 'long int'
i386-dis.c:12222 left shift of 1 by 31 places cannot be represented in type 'long int'
i386-dis.c:12222 signed integer overflow: 162254319 - -2147483648 cannot be represented in type 'long int'
* i386-dis.c (OP_E_memory): Don't cast to signed type when
negating.
(get32, get32s): Use unsigned types in shift expressions.
