x86: Don't display eiz with no scale
Change 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef(,%eiz,1),%rbx to 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef,%rbx in AT&T syntax and 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR [eiz*1+0x89abcdef] to 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR ds:0x89abcdef in Intel syntax. gas/ PR gas/26237 * testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Don't display eiz with no scale without base nor index registers.
This commit is contained in:
H.J. Lu
parent
56c1b507aa
commit
04c662e2b6
6 changed files with 28 additions and 14 deletions
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@ -1,3 +1,11 @@
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2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26237
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* testsuite/gas/i386/evex-no-scale-64.d: Updated.
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* testsuite/gas/i386/addr32.d: Likewise.
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* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
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* testsuite/gas/i386/x86-64-addr32.d: Likewise.
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2020-07-15 Nick Clifton <nickc@redhat.com>
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* write.c (create_note_reloc): Add desc2_size parameter. Zero out
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@ -10,5 +10,5 @@ Disassembly of section .text:
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+[a-f0-9]+: 62 f1 7c 48 28 04 05 40 00 00 00 vmovaps 0x40\(,%rax,1\),%zmm0
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+[a-f0-9]+: 62 f1 7c 48 28 04 25 40 00 00 00 vmovaps 0x40,%zmm0
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+[a-f0-9]+: 67 62 f1 7c 48 28 04 05 40 00 00 00 vmovaps 0x40\(,%eax,1\),%zmm0
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+[a-f0-9]+: 67 62 f1 7c 48 28 04 25 40 00 00 00 vmovaps 0x40\(,%eiz,1\),%zmm0
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+[a-f0-9]+: 67 62 f1 7c 48 28 04 25 40 00 00 00 vmovaps 0x40,%zmm0
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+[a-f0-9]+: 62 f1 7c 48 28 04 25 40 00 00 00 vmovaps 0x40,%zmm0
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@ -11,15 +11,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 48 8d 80 00 00 00 00[ ]+lea[ ]+rax,\[eax\+0x0\].*
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[ ]*[a-f0-9]+: 67 49 8d 80 00 00 00 00[ ]+lea[ ]+rax,\[r8d\+0x0\].*
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[ ]*[a-f0-9]+: 67 48 8d 05 00 00 00 00[ ]+lea[ ]+rax,\[eip\+0x0\].*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00 lea[ ]+rax,\[eiz\*1\+0x0\].*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00 lea[ ]+rax,ds:0x0 .*
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[ ]*[a-f0-9]+: 67 a0 98 08 60 00 addr32 mov al,ds:0x600898
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[ ]*[a-f0-9]+: 67 66 a1 98 08 60 00 addr32 mov ax,ds:0x600898
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[ ]*[a-f0-9]+: 67 a1 98 08 60 00 addr32 mov eax,ds:0x600898
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov rax,ds:0x600898
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov rax,ds:0x800898
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+rbx,QWORD PTR \[eiz\*1\+0x800898\]
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+rbx,QWORD PTR ds:0x800898
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[ ]*[a-f0-9]+: 67 48 a1 ef cd ab 89 addr32 mov rax,ds:0x89abcdef
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 ef cd ab 89 mov[ ]+rbx,QWORD PTR \[eiz\*1\+0x89abcdef\]
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 ef cd ab 89 mov[ ]+rbx,QWORD PTR ds:0x89abcdef
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[ ]*[a-f0-9]+: 67 48 b8 ef cd ab 89 00 00 00 00 addr32 movabs rax,0x89abcdef
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[ ]*[a-f0-9]+: 67 48 bb ef cd ab 89 00 00 00 00 addr32 movabs rbx,0x89abcdef
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov ds:0x600898,al
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@ -27,9 +27,9 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov ds:0x600898,eax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov ds:0x600898,rax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov ds:0x800898,rax
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+QWORD PTR \[eiz\*1\+0x800898\],rbx
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+QWORD PTR ds:0x800898,rbx
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[ ]*[a-f0-9]+: 67 48 a3 ef cd ab 89 addr32 mov ds:0x89abcdef,rax
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[ ]*[a-f0-9]+: 67 48 89 1c 25 ef cd ab 89 mov[ ]+QWORD PTR \[eiz\*1\+0x89abcdef\],rbx
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*1\+0xff332211\],eax
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[ ]*[a-f0-9]+: 67 48 89 1c 25 ef cd ab 89 mov[ ]+QWORD PTR ds:0x89abcdef,rbx
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+DWORD PTR ds:0xff332211,eax
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*2\+0xff332211\],eax
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#pass
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@ -10,15 +10,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 48 8d 80 00 00 00 00[ ]+lea[ ]+0x0\(%eax\),%rax.*
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[ ]*[a-f0-9]+: 67 49 8d 80 00 00 00 00[ ]+lea[ ]+0x0\(%r8d\),%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 05 00 00 00 00[ ]+lea[ ]+0x0\(%eip\),%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0\(,%eiz,1\),%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%rax.*
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[ ]*[a-f0-9]+: 67 a0 98 08 60 00 addr32 mov 0x600898,%al
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[ ]*[a-f0-9]+: 67 66 a1 98 08 60 00 addr32 mov 0x600898,%ax
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[ ]*[a-f0-9]+: 67 a1 98 08 60 00 addr32 mov 0x600898,%eax
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov 0x600898,%rax
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov 0x800898,%rax
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+0x800898\(,%eiz,1\),%rbx
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+0x800898,%rbx
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[ ]*[a-f0-9]+: 67 48 a1 ef cd ab 89 addr32 mov 0x89abcdef,%rax
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 ef cd ab 89 mov[ ]+0x89abcdef\(,%eiz,1\),%rbx
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 ef cd ab 89 mov[ ]+0x89abcdef,%rbx
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[ ]*[a-f0-9]+: 67 48 b8 ef cd ab 89 00 00 00 00 addr32 movabs \$0x89abcdef,%rax
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[ ]*[a-f0-9]+: 67 48 bb ef cd ab 89 00 00 00 00 addr32 movabs \$0x89abcdef,%rbx
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov %al,0x600898
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@ -26,9 +26,9 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov %eax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov %rax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov %rax,0x800898
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+%rbx,0x800898\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+%rbx,0x800898
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[ ]*[a-f0-9]+: 67 48 a3 ef cd ab 89 addr32 mov %rax,0x89abcdef
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[ ]*[a-f0-9]+: 67 48 89 1c 25 ef cd ab 89 mov[ ]+%rbx,0x89abcdef\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+%eax,0xff332211\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 48 89 1c 25 ef cd ab 89 mov[ ]+%rbx,0x89abcdef
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+%eax,0xff332211
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+%eax,0xff332211\(,%eiz,2\)
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#pass
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@ -1,3 +1,9 @@
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2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26237
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* i386-dis.c (OP_E_memory): Don't display eiz with no scale
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without base nor index registers.
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2020-07-15 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (putop): Move 'V' and 'W' handling.
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@ -11818,7 +11818,7 @@ OP_E_memory (int bytemode, int sizeflag)
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/* Without base nor index registers, zero-extend the
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lower 32-bit displacement to 64 bits. */
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disp = (unsigned int) disp;
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needindex = 1;
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needindex = scale;
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}
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needaddr32 = 1;
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}
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