aarch64: Add base support for Armv8-R
This patch adds the basic infrastructure needed to support Armv8-R in AArch64 binutils: new command-line flags, new feature bits, a new BFD architecture, and support for differentiating between architecture variants in the disassembler. The new command-line options added by this patch are -march=armv8-r in GAS and -m aarch64:armv8-r in objdump. The disassembler support is necessary since Armv8-R AArch64 introduces a system register (VSCTLR_EL2) which shares an encoding with a different system register (TTBR0_EL2) in Armv8-A. This also allows us to use the correct preferred disassembly for the new DFB alias introduced in Armv8-R. bfd/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * archures.c (bfd_mach_aarch64_8R): New. * bfd-in2.h: Regenerate. * cpu-aarch64.c (bfd_aarch64_arch_v8_r): New. (bfd_aarch64_arch_ilp32): Update tail pointer. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_archs): Add armv8-r. * doc/c-aarch64.texi: Document -march=armv8-r. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_A): New. (AARCH64_FEATURE_V8_R): New. (AARCH64_ARCH_V8): Include new A-profile feature bit. (AARCH64_ARCH_V8_R): New. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (arch_variant): New. (determine_disassembling_preference): Disassemble according to arch variant. (select_aarch64_variant): New. (print_insn_aarch64): Set feature set.
This commit is contained in:
Alex Coplan
parent
7ba115508a
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95830c988a
11 changed files with 76 additions and 3 deletions
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@ -1,3 +1,10 @@
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2020-09-08 Alex Coplan <alex.coplan@arm.com>
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* archures.c (bfd_mach_aarch64_8R): New.
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* bfd-in2.h: Regenerate.
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* cpu-aarch64.c (bfd_aarch64_arch_v8_r): New.
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(bfd_aarch64_arch_ilp32): Update tail pointer.
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2020-09-08 Alan Modra <amodra@gmail.com>
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PR 13250
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@ -530,6 +530,7 @@ DESCRIPTION
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.#define bfd_mach_tilegx32 2
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. bfd_arch_aarch64, {* AArch64. *}
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.#define bfd_mach_aarch64 0
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.#define bfd_mach_aarch64_8R 1
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.#define bfd_mach_aarch64_ilp32 32
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. bfd_arch_nios2, {* Nios II. *}
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.#define bfd_mach_nios2 0
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@ -1930,6 +1930,7 @@ enum bfd_architecture
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#define bfd_mach_tilegx32 2
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bfd_arch_aarch64, /* AArch64. */
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#define bfd_mach_aarch64 0
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#define bfd_mach_aarch64_8R 1
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#define bfd_mach_aarch64_ilp32 32
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bfd_arch_nios2, /* Nios II. */
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#define bfd_mach_nios2 0
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@ -107,8 +107,12 @@ scan (const struct bfd_arch_info *info, const char *string)
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"aarch64", PRINT, 4, DEFAULT, compatible, scan, \
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bfd_arch_default_fill, NEXT, 0 }
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static const bfd_arch_info_type bfd_aarch64_arch_v8_r =
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N (bfd_mach_aarch64_8R, "aarch64:armv8-r", 64, FALSE, NULL);
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static const bfd_arch_info_type bfd_aarch64_arch_ilp32 =
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N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 32, FALSE, NULL);
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N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 32, FALSE,
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&bfd_aarch64_arch_v8_r);
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const bfd_arch_info_type bfd_aarch64_arch =
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N (0, "aarch64", 64, TRUE, &bfd_aarch64_arch_ilp32);
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@ -1,3 +1,8 @@
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2020-09-08 Alex Coplan <alex.coplan@arm.com>
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* config/tc-aarch64.c (aarch64_archs): Add armv8-r.
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* doc/c-aarch64.texi: Document -march=armv8-r.
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2020-09-07 Mark Wielaard <mark@klomp.org>
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* dwarf2dbg.c (add_line_strp): New function.
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@ -8997,6 +8997,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
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{"armv8.4-a", AARCH64_ARCH_V8_4},
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{"armv8.5-a", AARCH64_ARCH_V8_5},
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{"armv8.6-a", AARCH64_ARCH_V8_6},
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{"armv8-r", AARCH64_ARCH_V8_R},
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{NULL, AARCH64_ARCH_NONE}
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};
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@ -100,7 +100,7 @@ issue an error message if an attempt is made to assemble an
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instruction which will not execute on the target architecture. The
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following architecture names are recognized: @code{armv8-a},
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@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
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@code{armv8.5-a}, and @code{armv8.6-a}.
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@code{armv8.5-a}, @code{armv8.6-a}, and @code{armv8-r}.
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If both @option{-mcpu} and @option{-march} are specified, the
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assembler will use the setting for @option{-mcpu}. If neither are
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@ -1,3 +1,10 @@
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2020-09-08 Alex Coplan <alex.coplan@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_V8_A): New.
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(AARCH64_FEATURE_V8_R): New.
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(AARCH64_ARCH_V8): Include new A-profile feature bit.
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(AARCH64_ARCH_V8_R): New.
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2020-09-02 Alan Modra <amodra@gmail.com>
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* opcode/v850.h (struct v850_operand <insert>): Make param op an
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@ -40,6 +40,7 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */
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#define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */
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#define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */
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#define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */
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#define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */
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#define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */
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#define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */
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@ -48,6 +49,7 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9)
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#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10)
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#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
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#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
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#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
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#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
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#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
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@ -90,7 +92,8 @@ typedef uint32_t aarch64_insn;
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/* Architectures are the sum of the base and extensions. */
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#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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AARCH64_FEATURE_FP \
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AARCH64_FEATURE_V8_A \
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| AARCH64_FEATURE_FP \
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| AARCH64_FEATURE_SIMD)
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#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
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AARCH64_FEATURE_CRC \
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@ -125,6 +128,9 @@ typedef uint32_t aarch64_insn;
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AARCH64_FEATURE_V8_6 \
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| AARCH64_FEATURE_BFLOAT16 \
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| AARCH64_FEATURE_I8MM)
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#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
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AARCH64_FEATURE_V8_R) \
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& ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
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#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
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#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
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@ -1,3 +1,11 @@
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2020-09-08 Alex Coplan <alex.coplan@arm.com>
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* aarch64-dis.c (arch_variant): New.
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(determine_disassembling_preference): Disassemble according to
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arch variant.
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(select_aarch64_variant): New.
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(print_insn_aarch64): Set feature set.
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2020-09-02 Alan Modra <amodra@gmail.com>
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* v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
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@ -35,6 +35,7 @@ enum map_type
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MAP_DATA
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};
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static aarch64_feature_set arch_variant; /* See select_aarch64_variant. */
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static enum map_type last_type;
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static int last_mapping_sym = -1;
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static bfd_vma last_stop_offset = 0;
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@ -2690,6 +2691,13 @@ determine_disassembling_preference (struct aarch64_inst *inst,
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DEBUG_TRACE ("skip %s as base opcode not match", alias->name);
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continue;
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}
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if (!AARCH64_CPU_HAS_FEATURE (arch_variant, *alias->avariant))
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{
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DEBUG_TRACE ("skip %s: we're missing features", alias->name);
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continue;
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}
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/* No need to do any complicated transformation on operands, if the alias
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opcode does not have any operand. */
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if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value)
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@ -3360,6 +3368,24 @@ get_sym_code_type (struct disassemble_info *info, int n,
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return FALSE;
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}
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/* Set the feature bits in arch_variant in order to get the correct disassembly
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for the chosen architecture variant.
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Currently we only restrict disassembly for Armv8-R and otherwise enable all
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non-R-profile features. */
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static void
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select_aarch64_variant (unsigned mach)
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{
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switch (mach)
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{
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case bfd_mach_aarch64_8R:
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arch_variant = AARCH64_ARCH_V8_R;
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break;
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default:
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arch_variant = AARCH64_ANY & ~(AARCH64_FEATURE_V8_R);
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}
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}
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/* Entry-point of the AArch64 disassembler. */
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int
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@ -3374,6 +3400,7 @@ print_insn_aarch64 (bfd_vma pc,
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unsigned int size = 4;
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unsigned long data;
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aarch64_operand_error errors;
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static bfd_boolean set_features;
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if (info->disassembler_options)
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{
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@ -3385,6 +3412,12 @@ print_insn_aarch64 (bfd_vma pc,
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info->disassembler_options = NULL;
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}
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if (!set_features)
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{
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select_aarch64_variant (info->mach);
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set_features = TRUE;
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}
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/* Aarch64 instructions are always little-endian */
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info->endian_code = BFD_ENDIAN_LITTLE;
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