For performance reasons it is important to write the full 64 bits of
an FPR target reg even when dealing with 32 bit values. So we chose
lder over ler for 32 bit float register moves. lder zero-extends the
32 bit value from the source reg to 64 bit in the target. However,
since it actually doesn't matter whether we write the upper 32 bits
with zeros or with any other garbage we can also use ldr instead. It
is bit shorter and therefore will do good for I-Cache usage.
gcc/ChangeLog:
2016-04-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/2964.md ("z13_unit_fxu", "z13_0"): Remove lder.
* config/s390/s390.md ("movsi_larl", "*movsi_esa", "mov<mode>"):
Change lder to ldr.
* config/s390/vector.md ("mov<mode>"): Likewise.
From-SVN: r235627
This fixes an issue with the long displacement memory address
constraints S and T. These were defined to only accept long
displacement addresses. This is wrong since a memory constraint must
not reject an address with a 0 displacement. Reload relies on being
able to turn an invalid memory address into a valid one by reloading
the address into a base register. The S and T constraints would
reject such an address.
This isn't really a problem for the backend since we used the
constraints with that knowledge there but it is a problem for people
writing inline assemblies.
gcc/ChangeLog:
2016-04-29 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/constraints.md ("U", "W"): Invoke
s390_mem_constraint with "ZR" and "ZT".
* config/s390/s390.c (s390_check_qrst_address): Reject invalid
addresses when using LRA. Accept also short displacements for S
and T constraints. Do not check for long displacement target for
S and T constraints.
(s390_mem_constraint): Remove handling of U and W constraints.
* config/s390/s390.md (various patterns): Remove the short
displacement constraints (Q and R) if a long displacement
constraint is present. Add longdisp as required CPU capability.
* config/s390/vector.md: Likewise.
* config/s390/vx-builtins.md: Likewise.
From-SVN: r235626
The combine pass may conclude umulhisi3_imm pattern can accept also sign
extended 16-bit constants. This patch prohibits the combine in considering
this pattern as suitable.
gcc/
2016-04-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.h (UNSIGNED_INT12, UNSIGNED_INT16): Define.
* config/arc/arc.md (umulhisi3): Use arc_short_operand predicate.
(umulhisi3_imm): Update predicates and constraint letters.
(umulhisi3_reg): Declare instruction as commutative.
* config/arc/constraints.md (J12, J16): New constraints.
* config/arc/predicates.md (short_unsigned_const_operand): New
predicate.
(arc_short_operand): Likewise.
* testsuite/gcc.target/arc/umulsihi3_z.c: New file.
From-SVN: r235623
2016-04-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/13962
PR tree-optimization/65686
* tree-ssa-alias.h (ptrs_compare_unequal): Declare.
* tree-ssa-alias.c (ptrs_compare_unequal): New function
using PTA to compare pointers.
* match.pd: Add pattern for pointer equality compare simplification
using ptrs_compare_unequal.
* gcc.dg/uninit-pr65686.c: New testcase.
From-SVN: r235622
* config/i386/i386.md (Load+RegOp to Mov+MemOp peephole2):
Use SWI mode iterator. Use general_reg_operand predicate.
(Load+RegOp to Mov+MemOp peephole2 with vector regs): Split
peephole to MMX and SSE part. Use mmx_reg_operand and sse_reg_operand
predicates.
From-SVN: r235620
2016-04-28 Andrew MacLeod <amacleod@redhat.com>
* c-array-notation.c (fix_builtin_array_notation_fn): Fix final
argument to build_modify_expr in two cases.
From-SVN: r235614
If a call expression is executed in an independent goroutine via
use of a Go statement, mark it as concurrent.
Reviewed-on: https://go-review.googlesource.com/18700
From-SVN: r235608
- Rename "info_ptr" to "info", as in all other routines;
- Don't set fields to 0, the whole struct already is set to 0;
- Fix formatting a bit.
* config/rs6000/rs6000.c (compute_save_world_info): Rename info_ptr
to info. Don't initialize separate fields to 0. Clean up
formatting a bit.
From-SVN: r235606
Exports String_index_expression and adds the getter `string` that
returns the underlying string. This will be used to handle string
indexing different from array indexing in escape analysis.
Reviewed-on: https://go-review.googlesource.com/18545
From-SVN: r235602
* config/i386/i386.md (peephole2s for operations with memory inputs):
Use SWI mode iterator.
(peephole2s for operations with memory outputs): Ditto.
Do not check for stack checking probe.
(probe_stack): Remove expander.
From-SVN: r235601
* cvt.c (cp_get_callee): New.
* constexpr.c (get_function_named_in_call): Use it.
* cxx-pretty-print.c (postfix_expression): Use it.
* except.c (check_noexcept_r): Use it.
* method.c (check_nontriv): Use it.
* tree.c (build_aggr_init_expr): Use it.
* cp-tree.h: Declare it.
From-SVN: r235596
This makes it clearer this field is only for SPE.
* config/rs6000/rs6000.c (machine_function): Rename
insn_chain_scanned_p to spe_insn_chain_scanned_p.
(rs6000_stack_info): Adjust.
From-SVN: r235588
PR target/70821
* config/i386/sync.md (define_peephole2 *atomic_fetch_add_cmp<mode>):
Add new peephole2 where the first insn is *mov<mode>_or instead of
*mov<mode>_internal.
* gcc.target/i386/pr70821.c: New test.
From-SVN: r235586
Expanders do not have more elements in the operands array than declared
in the pattern. So, we cannot use operands[5] here. Instead just
declare and use another rtx.
PR target/70668
* config/nds32/nds32.md (casesi): Don't access the operands array
out of bounds.
From-SVN: r235583
This patch adds support for the signed and unsigned int versions of the
vec_adde altivec builtins from the Power Architecture 64-Bit ELF V2 ABI
OpenPOWER ABI for Linux Supplement (16 July 2015 Version 1.1). There are
many of the builtins that are missing and this is the first of a series
of patches to add them.
There aren't instructions for the int versions of vec_adde so the
output code is built from other built-ins that do have instructions
which in this case is just two vec_adds with a vec_and to ensure the
carry vector is comprised of only the values 0 or 1.
The new test cases are executable tests which verify that the generated
code produces expected values. C macros were used so that the same
test case could be used for both the signed and unsigned versions. An
extra executable test case is also included to ensure that the modified
support for the __int128 versions of vec_adde is not broken. The same
test case could not be used for both int and __int128 because of some
differences in loading and storing the vectors.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this ok for trunk?
[gcc]
2016-04-28 Bill Seurer <seurer@linux.vnet.ibm.com>
* config/rs6000/rs6000-builtin.def (vec_adde): Change vec_adde to a
special case builtin.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove
ALTIVEC_BUILTIN_VEC_ADDE.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
support for ALTIVEC_BUILTIN_VEC_ADDE.
* config/rs6000/rs6000.c (altivec_init_builtins): Add definition
for __builtin_vec_adde.
[gcc/testsuite]
2016-04-28 Bill Seurer <seurer@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-adde.c: New test.
* gcc.target/powerpc/vec-adde-int128.c: New test.
From-SVN: r235577
2016-04-28 Martin Jambor <mjambor@suse.cz>
* tree-cfg.c (verify_expr): Verify that local declarations belong to
this function. Call verify_expr on MEM_REFs and bases of other
handled_components.
From-SVN: r235570
The double precision floating point assist instructions are not
implementing the reverse double subtract instruction (drsub) found in
the FPX extension.
gcc/
2016-04-28 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (cpu_facility): Add fpx variant.
(subdf3): Prohibit use reverse sub when assist operations option
is enabled.
* config/arc/fpx.md (subdf3_insn, *dsubh_peep2_insn): Allow drsub
instructions only when FPX is enabled.
* testsuite/gcc.target/arc/trsub.c: New test.
From-SVN: r235562
* config/i386/i386.md (*fop_<mode>_1_mixed): Do not check for
mult_operator when calculating "type" attribute.
(*fop_<mode>_1_i387): Ditto.
(*fop_xf_1_i387): Ditto.
(x87 stack loads peephole2): Add "reg = op (mem, reg)" peephole2.
Use std::swap to swap operands. Use RTL expressions to generate
converted pattern.
From-SVN: r235561
