Add a soft floating point condition to the register recovery part of the code.
libitm/ChangeLog:
* config/loongarch/sjlj.S: Add a soft floating point condition to the
register recovery part of the code.
Generate assembly with .localentry,1 functions using @notoc calls.
This patch makes libgcc.a asm look the same as power10 pcrel as far as
toc/notoc is concerned.
Otherwise calling between functions that advertise as using the TOC
and those that don't, will require linker call stubs in statically
linked code.
gcc/
* config/rs6000/ppc-asm.h: Support __PCREL__ code.
libgcc/
* config/rs6000/morestack.S,
* config/rs6000/tramp.S: Support __PCREL__ code.
libitm/
* config/powerpc/sjlj.S: Support __PCREL__ code.
_ITM_beginTransaction is a 'returns_twice' function that saves x30
on the stack as part of gtm_jmpbuf (that is passed down to
GTM_begin_transaction), but the saved x30 is also used for return.
The return path should be protected so we don't leave an
ldp x29, x30, [sp]
ret
gadget in the code, so x30 is signed on function entry. This
exposes the signed address in the gtm_jmpbuf too. The jmpbuf does
not need a signed address since GTM_longjmp uses
ldp x29, x30, [x1]
br x30
and with BTI there is a BTI j at the _ITM_beginTransaction call site
where this jump returns. Using PAC does not hurt: the gtm_jmpbuf is
internal to libitm and its layout is only used by sjlj.S so the
signed address does not escape. Saving signed x30 into gtm_jmpbuf
provides a bit of extra protection, but more importantly it allows
adding the PAC-RET support without changing the existing code much.
In theory bti and pac-ret protection can be added unconditionally
since the instructions are in the nop space, in practice they
can cause trouble if some tooling does not understand the gnu
property note (e.g. old binutils) or some unwinder or debugger
does not understand the new dwarf op code used for pac-ret (e.g
old gdb). So the code is written to only support branch-protection
according to the code generation options.
libitm/ChangeLog:
* config/aarch64/sjlj.S: Add conditional pac-ret protection.
sjlj.S did not have the GNU property note markup and the BTI c
instructions that are necessary when it is built with branch
protection.
The notes are only added when libitm is built with branch
protection, because old linkers mishandle the note (merge
them incorrectly or emit warnings), the BTI instructions
are added unconditionally.
2020-07-09 Szabolcs Nagy <szabolcs.nagy@arm.com>
libitm/ChangeLog:
* config/aarch64/sjlj.S: Add BTI marking and related definitions,
and add BTI c to function entries.
sjlj.S only had the note on Linux, but it is supposed
to have it on FreeBSD too.
2020-07-09 Szabolcs Nagy <szabolcs.nagy@arm.com>
libitm/ChangeLog:
* config/aarch64/sjlj.S: Add stack note if __FreeBSD__ is defined.
The ldaddr macro in sjlj.S needs to be updated to support the FDPIC
model.
2019-09-10 Christophe Lyon <christophe.lyon@st.com>
libitm/
* config/arm/sjlj.S (ldaddr): Add FDPIC support.
From-SVN: r275584
libitm/
* config/powerpc/target.h (htm_available): Add support for
PPC_FEATURE2_HTM_NO_SUSPEND. Use __builtin_cpu_supports if available.
From-SVN: r267101
In glibc, sysdeps/i386/nptl/tls.h has
typedef struct
{
void *tcb; /* Pointer to the TCB. Not necessarily the
thread descriptor used by libpthread. */
dtv_t *dtv;
void *self; /* Pointer to the thread descriptor. */
int multiple_threads;
uintptr_t sysinfo;
uintptr_t stack_guard;
uintptr_t pointer_guard;
int gscope_flag;
int __glibc_reserved1;
/* Reservation of some values for the TM ABI. */
void *__private_tm[4];
/* GCC split stack support. */
void *__private_ss;
} tcbhead_t;
and sysdeps/x86_64/nptl/tls.h has
typedef struct
{
void *tcb; /* Pointer to the TCB. Not necessarily the
thread descriptor used by libpthread. */
dtv_t *dtv;
void *self; /* Pointer to the thread descriptor. */
int multiple_threads;
int gscope_flag;
uintptr_t sysinfo;
uintptr_t stack_guard;
uintptr_t pointer_guard;
unsigned long int vgetcpu_cache[2];
int __glibc_reserved1;
int __glibc_unused1;
/* Reservation of some values for the TM ABI. */
void *__private_tm[4];
/* GCC split stack support. */
void *__private_ss;
long int __glibc_reserved2;
/* Must be kept even if it is no longer used by glibc since programs,
like AddressSanitizer, depend on the size of tcbhead_t. */
__128bits __glibc_unused2[8][4] __attribute__ ((aligned (32)));
void *__padding[8];
} tcbhead_t;
The offsets of __private_tm are
i386: 36 bytes
x32: 48 bytes
x86_64: 80 bytes
and the offsets of pointer_guard are:
i386: 24 bytes
x32: 28 bytes
x86_64: 48 bytes
But config/linux/x86/tls.h had
#ifdef __x86_64__
#ifdef __LP64__
# define SEG_READ(OFS) "movq\t%%fs:(" #OFS "*8),%0"
# define SEG_WRITE(OFS) "movq\t%0,%%fs:(" #OFS "*8)"
# define SEG_DECODE_READ(OFS) SEG_READ(OFS) "\n\t" \
"rorq\t$17,%0\n\t" \
"xorq\t%%fs:48,%0"
# define SEG_ENCODE_WRITE(OFS) "xorq\t%%fs:48,%0\n\t" \
"rolq\t$17,%0\n\t" \
SEG_WRITE(OFS)
#else
// For X32.
# define SEG_READ(OFS) "movl\t%%fs:(" #OFS "*4),%0"
# define SEG_WRITE(OFS) "movl\t%0,%%fs:(" #OFS "*4)"
# define SEG_DECODE_READ(OFS) SEG_READ(OFS) "\n\t" \
"rorl\t$9,%0\n\t" \
"xorl\t%%fs:24,%0"
# define SEG_ENCODE_WRITE(OFS) "xorl\t%%fs:24,%0\n\t" \
"roll\t$9,%0\n\t" \
SEG_WRITE(OFS)
#endif
#else
# define SEG_READ(OFS) "movl\t%%gs:(" #OFS "*4),%0"
# define SEG_WRITE(OFS) "movl\t%0,%%gs:(" #OFS "*4)"
# define SEG_DECODE_READ(OFS) SEG_READ(OFS) "\n\t" \
"rorl\t$9,%0\n\t" \
"xorl\t%%gs:24,%0"
# define SEG_ENCODE_WRITE(OFS) "xorl\t%%gs:24,%0\n\t" \
"roll\t$9,%0\n\t" \
SEG_WRITE(OFS)
#endif
static inline struct gtm_thread *gtm_thr(void)
{
struct gtm_thread *r;
asm volatile (SEG_READ(10) : "=r"(r));
return r;
}
static inline void set_gtm_thr(struct gtm_thread *x)
{
asm volatile (SEG_WRITE(10) : : "r"(x));
}
static inline struct abi_dispatch *abi_disp(void)
{
struct abi_dispatch *r;
asm volatile (SEG_DECODE_READ(11) : "=r"(r));
return r;
}
static inline void set_abi_disp(struct abi_dispatch *x)
{
void *scratch;
asm volatile (SEG_ENCODE_WRITE(11) : "=r"(scratch) : "0"(x));
}
SEG_READ, SEG_WRITE, SEG_DECODE_READ and SEG_ENCODE_WRITE were correct
only for x86-64.
Update SEG_READ and SEG_WRITE to use the offset of __private_tm as base
and correct the offset of pointer_guard for x32. This patch doesn't
change ABI of libitm.
PR libitm/85988
* config/linux/x86/tls.h (SEG_READ): Use the offset of
__private_tm as base.
(SEG_WRITE): Likewise.
(SEG_ENCODE_WRITE): Correct the offset of pointer_guard for x32.
(gtm_thr): Replace SEG_READ(10) with SEG_READ(0).
(set_gtm_thr): Replace SEG_WRITE(10) with SEG_WRITE(0).
(abi_disp): Replace SEG_DECODE_READ(11) with SEG_DECODE_READ(1).
(set_abi_disp): Replace SEG_ENCODE_WRITE(11) with
SEG_ENCODE_WRITE(1).
From-SVN: r261491
Use unsigned integer to unwind shadow stack by replacing jle with jbe and
jg with ja.
PR target/85489
* config/x86/sjlj.S (GTM_longjmp): Replace jle/jg with jbe/ja.
From-SVN: r259559
Expand the gtm_jmpbuf structure by one word field to add
Intel CET support further. The code in sjlj.S already
allocates more space on the stack then gtm_jmpbuf needs.
Use this extra space to absorb the new field.
The structure is allocated on the stack in such a way
that eip/rsp field is overlapped with return address on
the stack. Locate the new field right before eip/rsp so
code that accesses buffer fields relative to address of
gtm_jmpbuf has its offsets unchanged.
* libitm/config/x86/target.h: Add new field (ssp).
* libitm/config/x86/sjlj.S: Change offsets.
From-SVN: r254907
The attached patch adds the a target specific attribute via the
new target macro TARGET_BEGIN_TRANSACTION_ATTRIBUTE to the
function begin_transaction(). S/390 uses this to set the
soft-float target attribute which is needed to fix a crash with
-m31.
As there seems to be no place in libitm to document internal macros like
USE_HTM_FASTPATH or the new macro, I've put the documentation in a
comment where the macro is used.
2016-03-03 Dominik Vogt <vogt@linux.vnet.ibm.com>
* config/s390/target.h (TARGET_BEGIN_TRANSACTION_ATTRIBUTE): Define
function attribute to disable floating point in begin_transaction() on
S/390.
* beginend.cc (begin_transaction): Use
TARGET_BEGIN_TRANSACTION_ATTRIBUTE.
From-SVN: r233929
On behalf of Szabolcs.Nagy@arm.com
2015-04-22 Gregor Richards <gregor.richards@uwaterloo.ca>
* config/arm/hwcap.cc: Use fcntl.h instead of sys/fcntl.h.
* config/linux/x86/tls.h: Only use __GLIBC_PREREQ if defined.
From-SVN: r222325
* libitm_i.h (gtm_thread): Assign an asm name to serial_lock.
(htm_fastpath): Assign an asm name.
* libitm.h (_ITM_codeProperties): Add non-ABI flags used by custom
HTM fast paths.
(_ITM_actions): Likewise.
* config/x86/target.h (HTM_CUSTOM_FASTPATH): Enable custom fastpath on
x86_64.
* config/x86/sjlj.S (_ITM_beginTransaction): Add custom HTM fast path.
* config/posix/rwlock.h (gtm_rwlock): Update comments. Move summary
field to the start of the structure.
* config/linux/rwlock.h (gtm_rwlock): Update comments.
* beginend.cc (gtm_thread::begin_transaction): Add retry policy
handling for custom HTM fast paths.
From-SVN: r202101
