arm-modes.def: Add new condition code mode CC_V to represent the overflow bit.
2016-08-24 Michael Collison <michael.collison@linaro.org> Michael Collison <michael.collison@arm.com> * config/arm/arm-modes.def: Add new condition code mode CC_V to represent the overflow bit. * config/arm/arm.c (maybe_get_arm_condition_code): Add support for CC_Vmode. (arm_gen_unlikely_cbranch): New function to generate common rtl conditional branches for overflow patterns. * config/arm/arm-protos.h: Add prototype for arm_gen_unlikely_cbranch. * config/arm/arm.md (addv<mode>4, add<mode>3_compareV, addsi3_compareV_upper): New patterns to support signed builtin overflow add operations. (uaddv<mode>4, add<mode>3_compareC, addsi3_compareV_upper): New patterns to support unsigned builtin add overflow operations. (subv<mode>4, sub<mode>3_compare1): New patterns to support signed builtin overflow subtract operations, (usubv<mode>4): New patterns to support unsigned builtin subtract overflow operations. (negvsi3, negvdi3, negdi2_compare, negsi2_carryin_compare): New patterns to support builtin overflow negate operations. * gcc.target/arm/builtin_saddl.c: New testcase. * gcc.target/arm/builtin_saddll.c: New testcase. * gcc.target/arm/builtin_uaddl.c: New testcase. * gcc.target/arm/builtin_uaddll.c: New testcase. * gcc.target/arm/builtin_ssubl.c: New testcase. * gcc.target/arm/builtin_ssubll.c: New testcase. * gcc.target/arm/builtin_usubl.c: New testcase. * gcc.target/arm/builtin_usubll.c: New testcase. Co-Authored-By: Michael Collison <michael.collison@arm.com> From-SVN: r239739
This commit is contained in:
Michael Collison
Michael Collison
parent
d5b5d21260
commit
c8cd469647
14 changed files with 532 additions and 0 deletions
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@ -1,3 +1,26 @@
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2016-08-24 Michael Collison <michael.collison@linaro.org>
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Michael Collison <michael.collison@arm.com>
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* config/arm/arm-modes.def: Add new condition code mode CC_V
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to represent the overflow bit.
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* config/arm/arm.c (maybe_get_arm_condition_code):
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Add support for CC_Vmode.
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(arm_gen_unlikely_cbranch): New function to generate common
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rtl conditional branches for overflow patterns.
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* config/arm/arm-protos.h: Add prototype for
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arm_gen_unlikely_cbranch.
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* config/arm/arm.md (addv<mode>4, add<mode>3_compareV,
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addsi3_compareV_upper): New patterns to support signed
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builtin overflow add operations.
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(uaddv<mode>4, add<mode>3_compareC, addsi3_compareV_upper):
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New patterns to support unsigned builtin add overflow operations.
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(subv<mode>4, sub<mode>3_compare1): New patterns to support signed
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builtin overflow subtract operations,
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(usubv<mode>4): New patterns to support unsigned builtin subtract
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overflow operations.
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(negvsi3, negvdi3, negdi2_compare, negsi2_carryin_compare): New patterns
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to support builtin overflow negate operations.
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2016-08-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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Revert
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@ -59,6 +59,7 @@ CC_MODE (CC_DGEU);
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CC_MODE (CC_DGTU);
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CC_MODE (CC_C);
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CC_MODE (CC_N);
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CC_MODE (CC_V);
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/* Vector modes. */
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VECTOR_MODES (INT, 4); /* V4QI V2HI */
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@ -54,6 +54,8 @@ extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high);
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extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
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bool high);
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#ifdef RTX_CODE
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extern void arm_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
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rtx label_ref);
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extern bool arm_vector_mode_supported_p (machine_mode);
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extern bool arm_small_register_classes_for_mode_p (machine_mode);
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extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
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@ -22992,6 +22992,8 @@ maybe_get_arm_condition_code (rtx comparison)
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{
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case LTU: return ARM_CS;
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case GEU: return ARM_CC;
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case NE: return ARM_CS;
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case EQ: return ARM_CC;
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default: return ARM_NV;
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}
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@ -23017,6 +23019,14 @@ maybe_get_arm_condition_code (rtx comparison)
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default: return ARM_NV;
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}
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case CC_Vmode:
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switch (comp_code)
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{
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case NE: return ARM_VS;
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case EQ: return ARM_VC;
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default: return ARM_NV;
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}
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case CCmode:
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switch (comp_code)
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{
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@ -30575,4 +30585,23 @@ arm_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT vcall_offset,
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return true;
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}
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/* Generate RTL for a conditional branch with rtx comparison CODE in
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mode CC_MODE. The destination of the unlikely conditional branch
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is LABEL_REF. */
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void
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arm_gen_unlikely_cbranch (enum rtx_code code, machine_mode cc_mode,
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rtx label_ref)
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{
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rtx x;
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x = gen_rtx_fmt_ee (code, VOIDmode,
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gen_rtx_REG (cc_mode, CC_REGNUM),
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const0_rtx);
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x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
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gen_rtx_LABEL_REF (VOIDmode, label_ref),
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pc_rtx);
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emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
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}
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#include "gt-arm.h"
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@ -547,6 +547,32 @@
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(set_attr "type" "multiple")]
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)
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(define_expand "addv<mode>4"
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[(match_operand:SIDI 0 "register_operand")
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(match_operand:SIDI 1 "register_operand")
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(match_operand:SIDI 2 "register_operand")
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(match_operand 3 "")]
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"TARGET_32BIT"
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{
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emit_insn (gen_add<mode>3_compareV (operands[0], operands[1], operands[2]));
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arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
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DONE;
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})
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(define_expand "uaddv<mode>4"
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[(match_operand:SIDI 0 "register_operand")
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(match_operand:SIDI 1 "register_operand")
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(match_operand:SIDI 2 "register_operand")
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(match_operand 3 "")]
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"TARGET_32BIT"
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{
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emit_insn (gen_add<mode>3_compareC (operands[0], operands[1], operands[2]));
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arm_gen_unlikely_cbranch (NE, CC_Cmode, operands[3]);
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DONE;
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})
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "s_register_operand" "")
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(plus:SI (match_operand:SI 1 "s_register_operand" "")
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@ -624,6 +650,165 @@
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]
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)
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(define_insn_and_split "adddi3_compareV"
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[(set (reg:CC_V CC_REGNUM)
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(ne:CC_V
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(plus:TI
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(sign_extend:TI (match_operand:DI 1 "register_operand" "r"))
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(sign_extend:TI (match_operand:DI 2 "register_operand" "r")))
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(sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
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(set (match_operand:DI 0 "register_operand" "=&r")
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(plus:DI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT"
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"#"
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"&& reload_completed"
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[(parallel [(set (reg:CC_C CC_REGNUM)
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(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
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(match_dup 1)))
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(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
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(parallel [(set (reg:CC_V CC_REGNUM)
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(ne:CC_V
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(plus:DI (plus:DI
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(sign_extend:DI (match_dup 4))
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(sign_extend:DI (match_dup 5)))
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(ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
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(plus:DI (sign_extend:DI
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(plus:SI (match_dup 4) (match_dup 5)))
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(ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
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(set (match_dup 3) (plus:SI (plus:SI
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(match_dup 4) (match_dup 5))
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(ltu:SI (reg:CC_C CC_REGNUM)
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(const_int 0))))])]
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"
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{
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operands[3] = gen_highpart (SImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[5] = gen_highpart (SImode, operands[2]);
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operands[2] = gen_lowpart (SImode, operands[2]);
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}"
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[(set_attr "conds" "set")
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(set_attr "length" "8")
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(set_attr "type" "multiple")]
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)
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(define_insn "addsi3_compareV"
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[(set (reg:CC_V CC_REGNUM)
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(ne:CC_V
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(plus:DI
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(sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
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(sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
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(sign_extend:DI (plus:SI (match_dup 1) (match_dup 2)))))
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(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT"
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"adds%?\\t%0, %1, %2"
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[(set_attr "conds" "set")
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(set_attr "type" "alus_sreg")]
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)
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(define_insn "*addsi3_compareV_upper"
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[(set (reg:CC_V CC_REGNUM)
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(ne:CC_V
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(plus:DI
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(plus:DI
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(sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
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(sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
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(ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
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(plus:DI (sign_extend:DI
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(plus:SI (match_dup 1) (match_dup 2)))
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(ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
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(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI
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(plus:SI (match_dup 1) (match_dup 2))
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
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"TARGET_32BIT"
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"adcs%?\\t%0, %1, %2"
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[(set_attr "conds" "set")
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(set_attr "type" "adcs_reg")]
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)
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(define_insn_and_split "adddi3_compareC"
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[(set (reg:CC_C CC_REGNUM)
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(ne:CC_C
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(plus:TI
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(zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
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(zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
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(zero_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
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(set (match_operand:DI 0 "register_operand" "=&r")
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(plus:DI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT"
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"#"
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"&& reload_completed"
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[(parallel [(set (reg:CC_C CC_REGNUM)
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(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
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(match_dup 1)))
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(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
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(parallel [(set (reg:CC_C CC_REGNUM)
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(ne:CC_C
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(plus:DI (plus:DI
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(zero_extend:DI (match_dup 4))
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(zero_extend:DI (match_dup 5)))
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(ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
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(plus:DI (zero_extend:DI
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(plus:SI (match_dup 4) (match_dup 5)))
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(ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
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(set (match_dup 3) (plus:SI
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(plus:SI (match_dup 4) (match_dup 5))
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(ltu:SI (reg:CC_C CC_REGNUM)
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(const_int 0))))])]
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"
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{
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operands[3] = gen_highpart (SImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[5] = gen_highpart (SImode, operands[2]);
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[2] = gen_lowpart (SImode, operands[2]);
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}"
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[(set_attr "conds" "set")
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(set_attr "length" "8")
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(set_attr "type" "multiple")]
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)
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(define_insn "*addsi3_compareC_upper"
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[(set (reg:CC_C CC_REGNUM)
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(ne:CC_C
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(plus:DI
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(plus:DI
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(zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
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(zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
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(ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
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(plus:DI (zero_extend:DI
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(plus:SI (match_dup 1) (match_dup 2)))
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(ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
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(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI
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(plus:SI (match_dup 1) (match_dup 2))
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
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"TARGET_32BIT"
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"adcs%?\\t%0, %1, %2"
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[(set_attr "conds" "set")
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(set_attr "type" "adcs_reg")]
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)
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(define_insn "addsi3_compareC"
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[(set (reg:CC_C CC_REGNUM)
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(ne:CC_C
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(plus:DI
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(zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
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(zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
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(zero_extend:DI
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(plus:SI (match_dup 1) (match_dup 2)))))
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(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT"
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"adds%?\\t%0, %1, %2"
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[(set_attr "conds" "set")
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(set_attr "type" "alus_sreg")]
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)
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(define_insn "addsi3_compare0"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV
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@ -873,6 +1058,75 @@
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(set_attr "type" "adcs_reg")]
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)
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(define_expand "subv<mode>4"
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[(match_operand:SIDI 0 "register_operand")
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(match_operand:SIDI 1 "register_operand")
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(match_operand:SIDI 2 "register_operand")
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(match_operand 3 "")]
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"TARGET_32BIT"
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{
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emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
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arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
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DONE;
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})
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(define_expand "usubv<mode>4"
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[(match_operand:SIDI 0 "register_operand")
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(match_operand:SIDI 1 "register_operand")
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(match_operand:SIDI 2 "register_operand")
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(match_operand 3 "")]
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"TARGET_32BIT"
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{
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emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
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arm_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
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DONE;
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})
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(define_insn_and_split "subdi3_compare1"
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[(set (reg:CC CC_REGNUM)
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(compare:CC
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(match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "register_operand" "r")))
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(set (match_operand:DI 0 "register_operand" "=&r")
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(minus:DI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT"
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"#"
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"&& reload_completed"
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[(parallel [(set (reg:CC CC_REGNUM)
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(compare:CC (match_dup 1) (match_dup 2)))
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(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
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(parallel [(set (reg:CC CC_REGNUM)
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(compare:CC (match_dup 4) (match_dup 5)))
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(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))])]
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{
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operands[3] = gen_highpart (SImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[5] = gen_highpart (SImode, operands[2]);
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operands[2] = gen_lowpart (SImode, operands[2]);
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}
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[(set_attr "conds" "set")
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(set_attr "length" "8")
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(set_attr "type" "multiple")]
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)
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(define_insn "subsi3_compare1"
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[(set (reg:CC CC_REGNUM)
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(compare:CC
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(match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "register_operand" "r")))
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(set (match_operand:SI 0 "register_operand" "=r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT"
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"subs%?\\t%0, %1, %2"
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[(set_attr "conds" "set")
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(set_attr "type" "alus_sreg")]
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)
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(define_insn "*subsi3_carryin"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r")
|
||||
(minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I")
|
||||
|
|
@ -4360,6 +4614,63 @@
|
|||
|
||||
;; Unary arithmetic insns
|
||||
|
||||
(define_expand "negvsi3"
|
||||
[(match_operand:SI 0 "register_operand")
|
||||
(match_operand:SI 1 "register_operand")
|
||||
(match_operand 2 "")]
|
||||
"TARGET_32BIT"
|
||||
{
|
||||
emit_insn (gen_subsi3_compare (operands[0], const0_rtx, operands[1]));
|
||||
arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
|
||||
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "negvdi3"
|
||||
[(match_operand:DI 0 "register_operand")
|
||||
(match_operand:DI 1 "register_operand")
|
||||
(match_operand 2 "")]
|
||||
"TARGET_ARM"
|
||||
{
|
||||
emit_insn (gen_negdi2_compare (operands[0], operands[1]));
|
||||
arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
|
||||
|
||||
DONE;
|
||||
})
|
||||
|
||||
|
||||
(define_insn_and_split "negdi2_compare"
|
||||
[(set (reg:CC CC_REGNUM)
|
||||
(compare:CC
|
||||
(const_int 0)
|
||||
(match_operand:DI 1 "register_operand" "0,r")))
|
||||
(set (match_operand:DI 0 "register_operand" "=r,&r")
|
||||
(minus:DI (const_int 0) (match_dup 1)))]
|
||||
"TARGET_ARM"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(parallel [(set (reg:CC CC_REGNUM)
|
||||
(compare:CC (const_int 0) (match_dup 1)))
|
||||
(set (match_dup 0) (minus:SI (const_int 0)
|
||||
(match_dup 1)))])
|
||||
(parallel [(set (reg:CC CC_REGNUM)
|
||||
(compare:CC (const_int 0) (match_dup 3)))
|
||||
(set (match_dup 2)
|
||||
(minus:SI
|
||||
(minus:SI (const_int 0) (match_dup 3))
|
||||
(ltu:SI (reg:CC_C CC_REGNUM)
|
||||
(const_int 0))))])]
|
||||
{
|
||||
operands[2] = gen_highpart (SImode, operands[0]);
|
||||
operands[0] = gen_lowpart (SImode, operands[0]);
|
||||
operands[3] = gen_highpart (SImode, operands[1]);
|
||||
operands[1] = gen_lowpart (SImode, operands[1]);
|
||||
}
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "length" "8")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_expand "negdi2"
|
||||
[(parallel
|
||||
[(set (match_operand:DI 0 "s_register_operand" "")
|
||||
|
|
@ -4400,6 +4711,20 @@
|
|||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*negsi2_carryin_compare"
|
||||
[(set (reg:CC CC_REGNUM)
|
||||
(compare:CC (const_int 0)
|
||||
(match_operand:SI 1 "s_register_operand" "r")))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (minus:SI (const_int 0)
|
||||
(match_dup 1))
|
||||
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
|
||||
"TARGET_ARM"
|
||||
"rscs\\t%0, %1, #0"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "type" "alus_imm")]
|
||||
)
|
||||
|
||||
(define_expand "negsi2"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "")
|
||||
(neg:SI (match_operand:SI 1 "s_register_operand" "")))]
|
||||
|
|
|
|||
|
|
@ -1,3 +1,15 @@
|
|||
2016-08-24 Michael Collison <michael.collison@linaro.org>
|
||||
Michael Collison <michael.collison@arm.com>
|
||||
|
||||
* gcc.target/arm/builtin_saddl.c: New testcase.
|
||||
* gcc.target/arm/builtin_saddll.c: New testcase.
|
||||
* gcc.target/arm/builtin_uaddl.c: New testcase.
|
||||
* gcc.target/arm/builtin_uaddll.c: New testcase.
|
||||
* gcc.target/arm/builtin_ssubl.c: New testcase.
|
||||
* gcc.target/arm/builtin_ssubll.c: New testcase.
|
||||
* gcc.target/arm/builtin_usubl.c: New testcase.
|
||||
* gcc.target/arm/builtin_usubll.c: New testcase.
|
||||
|
||||
2016-08-24 Uros Bizjak <ubizjak@gmail.com>
|
||||
|
||||
PR target/77270
|
||||
|
|
|
|||
17
gcc/testsuite/gcc.target/arm/builtin_saddl.c
Normal file
17
gcc/testsuite/gcc.target/arm/builtin_saddl.c
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-require-effective-target arm32 } */
|
||||
extern void overflow_handler ();
|
||||
|
||||
long overflow_add (long x, long y)
|
||||
{
|
||||
long r;
|
||||
|
||||
int ovr = __builtin_saddl_overflow (x, y, &r);
|
||||
if (ovr)
|
||||
overflow_handler ();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "adds" } } */
|
||||
18
gcc/testsuite/gcc.target/arm/builtin_saddll.c
Normal file
18
gcc/testsuite/gcc.target/arm/builtin_saddll.c
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-require-effective-target arm32 } */
|
||||
extern void overflow_handler ();
|
||||
|
||||
long long overflow_add (long long x, long long y)
|
||||
{
|
||||
long long r;
|
||||
|
||||
int ovr = __builtin_saddll_overflow (x, y, &r);
|
||||
if (ovr)
|
||||
overflow_handler ();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "adds" } } */
|
||||
/* { dg-final { scan-assembler "adcs" } } */
|
||||
17
gcc/testsuite/gcc.target/arm/builtin_ssubl.c
Normal file
17
gcc/testsuite/gcc.target/arm/builtin_ssubl.c
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-require-effective-target arm32 } */
|
||||
extern void overflow_handler ();
|
||||
|
||||
long overflow_sub (long x, long y)
|
||||
{
|
||||
long r;
|
||||
|
||||
int ovr = __builtin_ssubl_overflow (x, y, &r);
|
||||
if (ovr)
|
||||
overflow_handler ();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "subs" } } */
|
||||
18
gcc/testsuite/gcc.target/arm/builtin_ssubll.c
Normal file
18
gcc/testsuite/gcc.target/arm/builtin_ssubll.c
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-require-effective-target arm32 } */
|
||||
extern void overflow_handler ();
|
||||
|
||||
long long overflow_sub (long long x, long long y)
|
||||
{
|
||||
long long r;
|
||||
|
||||
int ovr = __builtin_ssubll_overflow (x, y, &r);
|
||||
if (ovr)
|
||||
overflow_handler ();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "subs" } } */
|
||||
/* { dg-final { scan-assembler "sbcs" } } */
|
||||
17
gcc/testsuite/gcc.target/arm/builtin_uaddl.c
Normal file
17
gcc/testsuite/gcc.target/arm/builtin_uaddl.c
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-require-effective-target arm32 } */
|
||||
extern void overflow_handler ();
|
||||
|
||||
unsigned long overflow_add (unsigned long x, unsigned long y)
|
||||
{
|
||||
unsigned long r;
|
||||
|
||||
int ovr = __builtin_uaddl_overflow (x, y, &r);
|
||||
if (ovr)
|
||||
overflow_handler ();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "adds" } } */
|
||||
18
gcc/testsuite/gcc.target/arm/builtin_uaddll.c
Normal file
18
gcc/testsuite/gcc.target/arm/builtin_uaddll.c
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-require-effective-target arm32 } */
|
||||
extern void overflow_handler ();
|
||||
|
||||
unsigned long long overflow_add (unsigned long long x, unsigned long long y)
|
||||
{
|
||||
unsigned long long r;
|
||||
|
||||
int ovr = __builtin_uaddll_overflow (x, y, &r);
|
||||
if (ovr)
|
||||
overflow_handler ();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "adds" } } */
|
||||
/* { dg-final { scan-assembler "adcs" } } */
|
||||
17
gcc/testsuite/gcc.target/arm/builtin_usubl.c
Normal file
17
gcc/testsuite/gcc.target/arm/builtin_usubl.c
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-require-effective-target arm32 } */
|
||||
extern void overflow_handler ();
|
||||
|
||||
unsigned long overflow_sub (unsigned long x, unsigned long y)
|
||||
{
|
||||
unsigned long r;
|
||||
|
||||
int ovr = __builtin_usubl_overflow (x, y, &r);
|
||||
if (ovr)
|
||||
overflow_handler ();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "subs" } } */
|
||||
18
gcc/testsuite/gcc.target/arm/builtin_usubll.c
Normal file
18
gcc/testsuite/gcc.target/arm/builtin_usubll.c
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-require-effective-target arm32 } */
|
||||
extern void overflow_handler ();
|
||||
|
||||
unsigned long long overflow_sub (unsigned long long x, unsigned long long y)
|
||||
{
|
||||
unsigned long long r;
|
||||
|
||||
int ovr = __builtin_usubll_overflow (x, y, &r);
|
||||
if (ovr)
|
||||
overflow_handler ();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "subs" } } */
|
||||
/* { dg-final { scan-assembler "sbcs" } } */
|
||||
Loading…
Add table
Reference in a new issue