AVX512FP16: Enhance vector shuffle builtins
Support HFmode vector shuffle by creating HImode subreg when expanding permutation expr. gcc/ChangeLog: * config/i386/i386-expand.c (ix86_expand_vec_perm): Convert HFmode input operand to HImode. (ix86_vectorize_vec_perm_const): Likewise. * config/i386/sse.md (*avx512bw_permvar_truncv16siv16hi_1_hf): New define_insn. (*avx512f_permvar_truncv8siv8hi_1_hf): Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512fp16-builtin_shuffle-1.c: New test. * gcc.target/i386/avx512fp16-pr101846.c: Ditto. * gcc.target/i386/avx512fp16-pr94680.c: Ditto.
This commit is contained in:
Hongyu Wang
parent
147ed0184f
commit
be072bfa5b
5 changed files with 280 additions and 1 deletions
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@ -4846,6 +4846,16 @@ ix86_expand_vec_perm (rtx operands[])
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e = GET_MODE_UNIT_SIZE (mode);
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gcc_assert (w <= 64);
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/* For HF mode vector, convert it to HI using subreg. */
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if (GET_MODE_INNER (mode) == HFmode)
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{
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machine_mode orig_mode = mode;
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mode = mode_for_vector (HImode, w).require ();
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target = lowpart_subreg (mode, target, orig_mode);
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op0 = lowpart_subreg (mode, op0, orig_mode);
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op1 = lowpart_subreg (mode, op1, orig_mode);
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}
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if (TARGET_AVX512F && one_operand_shuffle)
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{
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rtx (*gen) (rtx, rtx, rtx) = NULL;
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@ -21139,6 +21149,20 @@ ix86_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
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unsigned int i, nelt, which;
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bool two_args;
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/* For HF mode vector, convert it to HI using subreg. */
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if (GET_MODE_INNER (vmode) == HFmode)
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{
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machine_mode orig_mode = vmode;
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vmode = mode_for_vector (HImode,
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GET_MODE_NUNITS (vmode)).require ();
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if (target)
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target = lowpart_subreg (vmode, target, orig_mode);
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if (op0)
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op0 = lowpart_subreg (vmode, op0, orig_mode);
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if (op1)
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op1 = lowpart_subreg (vmode, op1, orig_mode);
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}
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d.target = target;
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d.op0 = op0;
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d.op1 = op1;
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@ -12757,6 +12757,33 @@
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(truncate:V16HI (match_dup 1)))]
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"operands[1] = lowpart_subreg (V16SImode, operands[1], V32HImode);")
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(define_insn_and_split "*avx512bw_permvar_truncv16siv16hi_1_hf"
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[(set (match_operand:V16HF 0 "nonimmediate_operand")
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(vec_select:V16HF
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(subreg:V32HF
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(unspec:V32HI
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[(match_operand:V32HI 1 "register_operand")
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(match_operand:V32HI 2 "permvar_truncate_operand")]
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UNSPEC_VPERMVAR) 0)
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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(const_int 4) (const_int 5)
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(const_int 6) (const_int 7)
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(const_int 8) (const_int 9)
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(const_int 10) (const_int 11)
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)])))]
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"TARGET_AVX512BW && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(truncate:V16HI (match_dup 1)))]
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{
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operands[0] = lowpart_subreg (V16HImode, operands[0], V16HFmode);
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operands[1] = lowpart_subreg (V16SImode, operands[1], V32HImode);
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})
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(define_insn_and_split "*avx512f_permvar_truncv8siv8hi_1"
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[(set (match_operand:V8HI 0 "nonimmediate_operand")
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(vec_select:V8HI
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@ -12775,6 +12802,28 @@
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(truncate:V8HI (match_dup 1)))]
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"operands[1] = lowpart_subreg (V8SImode, operands[1], V16HImode);")
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(define_insn_and_split "*avx512f_permvar_truncv8siv8hi_1_hf"
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[(set (match_operand:V8HF 0 "nonimmediate_operand")
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(vec_select:V8HF
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(subreg:V16HF
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(unspec:V16HI
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[(match_operand:V16HI 1 "register_operand")
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(match_operand:V16HI 2 "permvar_truncate_operand")]
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UNSPEC_VPERMVAR) 0)
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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(const_int 4) (const_int 5)
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(const_int 6) (const_int 7)])))]
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"TARGET_AVX512VL && TARGET_AVX512BW && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(truncate:V8HI (match_dup 1)))]
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{
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operands[0] = lowpart_subreg (V8HImode, operands[0], V8HFmode);
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operands[1] = lowpart_subreg (V8SImode, operands[1], V16HImode);
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})
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(define_insn_and_split "*avx512f_vpermvar_truncv8div8si_1"
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[(set (match_operand:V8SI 0 "nonimmediate_operand")
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(vec_select:V8SI
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@ -15787,12 +15836,15 @@
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(define_mode_iterator VEC_PERM_AVX2
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[V16QI V8HI V4SI V2DI V4SF V2DF
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(V8HF "TARGET_AVX512FP16")
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(V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2")
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(V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2")
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(V8SF "TARGET_AVX2") (V4DF "TARGET_AVX2")
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(V16HF "TARGET_AVX512FP16")
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(V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F")
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(V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F")
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(V32HI "TARGET_AVX512BW") (V64QI "TARGET_AVX512VBMI")])
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(V32HI "TARGET_AVX512BW") (V64QI "TARGET_AVX512VBMI")
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(V32HF "TARGET_AVX512FP16")])
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(define_expand "vec_perm<mode>"
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[(match_operand:VEC_PERM_AVX2 0 "register_operand")
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86
gcc/testsuite/gcc.target/i386/avx512fp16-builtin_shuffle-1.c
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86
gcc/testsuite/gcc.target/i386/avx512fp16-builtin_shuffle-1.c
Normal file
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@ -0,0 +1,86 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
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/* { dg-final { scan-assembler-not "movw" } } */
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/* { dg-final { scan-assembler-times "vpermi2w" 3 } } */
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/* { dg-final { scan-assembler-times "vpermw" 6 } } */
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/* { dg-final { scan-assembler-times "vpshufb" 3 } } */
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/* { dg-final { scan-assembler-times "vpermt2w" 6 } } */
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typedef _Float16 v32hf __attribute__((vector_size (64)));
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typedef _Float16 v16hf __attribute__((vector_size (32)));
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typedef _Float16 v8hf __attribute__((vector_size (16)));
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typedef short v32hi __attribute__((vector_size (64)));
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typedef short v16hi __attribute__((vector_size (32)));
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typedef short v8hi __attribute__((vector_size (16)));
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#define PERM_CONST_RANDOM_v32hi \
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{ 0, 21, 15, 9, 43, 25, 37, 48, \
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8, 16, 27, 51, 30, 12, 6, 46, \
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34, 3, 11, 5, 17, 53, 26, 39, \
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2, 18, 40, 61, 19, 4, 50, 29 }
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#define PERM_CONST_RANDOM_RANGE32_v32hi \
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{ 0, 21, 10, 23, 8, 18, 7, 19, \
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4, 25, 3, 31, 5, 22, 11, 17, \
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9, 20, 2, 24, 1, 30, 12, 27, \
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13, 28, 6, 29, 14, 16, 15, 23 }
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#define PERM_CONST_RANDOM_v16hi \
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{ 0, 21, 15, 9, 13, 25, 30, 18, \
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8, 16, 17, 11, 4, 22, 6, 7 }
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#define PERM_CONST_RANDOM_RANGE16_v16hi \
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{ 0, 9, 1, 12, 4, 15, 7, 13, \
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3, 10, 6, 14, 5, 8, 2, 11 }
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#define PERM_CONST_RANDOM_v8hi \
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{ 0, 14, 15, 9, 13, 2, 3, 5 }
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#define PERM_CONST_RANDOM_RANGE8_v8hi \
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{ 0, 7, 2, 5, 3, 4, 1, 6 }
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#define PERM_CONST_RANDOM(size) \
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PERM_CONST_RANDOM_v##size##hi
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#define PERM_CONST_RANDOM_RANGE(size) \
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PERM_CONST_RANDOM_RANGE##size##_v##size##hi
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#define SHUFFLE_CONST_RANDOM(type, itype, size) \
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type foo_##type##shuffle_2param_const_random (type a, type b) \
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{ \
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return __builtin_shuffle (a, b, \
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(itype) PERM_CONST_RANDOM (size)); \
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} \
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type foo_##type##shuffle_2param_const_random_range (type a, type b) \
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{ \
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return __builtin_shuffle (a, b, \
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(itype) PERM_CONST_RANDOM_RANGE (size)); \
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} \
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type foo_##type##shuffle_1param_const_random (type a) \
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{ \
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return __builtin_shuffle (a, \
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(itype) PERM_CONST_RANDOM (size)); \
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} \
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type foo_##type##shuffle_1param_const_random_range (type a) \
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{ \
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return __builtin_shuffle (a, \
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(itype) PERM_CONST_RANDOM_RANGE (size)); \
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}
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#define SHUFFLE_VEC_INDEX(type, itype) \
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type foo##type##itype##shuffle_2param_vec (type a, type b, itype c) \
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{ \
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return __builtin_shuffle (a, b, c); \
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} \
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type foo##type##itype##shuffle_1param_vec (type a, itype c) \
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{ \
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return __builtin_shuffle (a, c); \
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}
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SHUFFLE_CONST_RANDOM (v32hf, v32hi, 32)
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SHUFFLE_CONST_RANDOM (v16hf, v16hi, 16)
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SHUFFLE_CONST_RANDOM (v8hf, v8hi, 8)
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SHUFFLE_VEC_INDEX (v32hf, v32hi)
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SHUFFLE_VEC_INDEX (v16hf, v16hi)
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SHUFFLE_VEC_INDEX (v8hf, v8hi)
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56
gcc/testsuite/gcc.target/i386/avx512fp16-pr101846.c
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56
gcc/testsuite/gcc.target/i386/avx512fp16-pr101846.c
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@ -0,0 +1,56 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
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/* { dg-final { scan-assembler-times "vpmovzxwd" "3" } } */
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/* { dg-final { scan-assembler-times "vpmovdw" "3" } } */
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typedef _Float16 v32hf __attribute__((vector_size (64)));
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typedef _Float16 v16hf __attribute__((vector_size (32)));
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typedef _Float16 v8hf __attribute__((vector_size (16)));
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typedef _Float16 v4hf __attribute__((vector_size (8)));
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typedef short v4hi __attribute__((vector_size (8)));
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typedef short v8hi __attribute__((vector_size (16)));
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#define PERM_CONST_INTERLEAVE_v32hi \
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0, 16, 1, 17, 2, 18, 3, 19, \
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4, 20, 5, 21, 6, 22, 7, 23, \
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8, 24, 9, 25, 10, 26, 11, 27, \
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12, 28, 13, 29, 14, 30, 15, 31
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#define PERM_CONST_INTERLEAVE_v16hi \
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0, 8, 1, 9, 2, 10, 3, 11, \
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4, 12, 5, 13, 6, 14, 7, 15
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#define PERM_CONST_INTERLEAVE_v8hi \
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0, 4, 1, 5, 2, 6, 3, 7
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#define PERM_CONST_TRUNCATE_v32hi \
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0, 2, 4, 6, 8, 10, 12, 14, \
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16, 18, 20, 22, 24, 26, 28, 30
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#define PERM_CONST_TRUNCATE_v16hi \
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0, 2, 4, 6, 8, 10, 12, 14
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#define PERM_CONST_TRUNCATE_v8hi \
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0, 2, 4, 6
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#define PERM_CONST_INTERLEAVE(size) \
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PERM_CONST_INTERLEAVE_v##size##hi
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#define PERM_CONST_TRUNCATE(size) \
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PERM_CONST_TRUNCATE_v##size##hi
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#define SHUFFLE_CONST_INTERLEAVE(type, rtype, size) \
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rtype foo_##type##shufflevector_const_interleave (type a) \
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{ \
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return __builtin_shufflevector (a, (type) {}, \
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PERM_CONST_INTERLEAVE (size)); \
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} \
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type foo_##type##shufflevector_const_trunc (rtype a) \
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{ \
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return __builtin_shufflevector (a, a, \
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PERM_CONST_TRUNCATE (size)); \
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}
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SHUFFLE_CONST_INTERLEAVE (v16hf, v32hf, 32)
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SHUFFLE_CONST_INTERLEAVE (v8hf, v16hf, 16)
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SHUFFLE_CONST_INTERLEAVE (v4hf, v8hf, 8)
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61
gcc/testsuite/gcc.target/i386/avx512fp16-pr94680.c
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61
gcc/testsuite/gcc.target/i386/avx512fp16-pr94680.c
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@ -0,0 +1,61 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
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/* { dg-final { scan-assembler-times "vmovdqa" 4 } } */
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/* { dg-final { scan-assembler-times "vmovq" 2 } } */
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typedef _Float16 v32hf __attribute__((vector_size (64)));
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typedef _Float16 v16hf __attribute__((vector_size (32)));
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typedef _Float16 v8hf __attribute__((vector_size (16)));
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typedef short v32hi __attribute__((vector_size (64)));
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typedef short v16hi __attribute__((vector_size (32)));
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typedef short v8hi __attribute__((vector_size (16)));
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#define PERM_CONST_CONCAT0_v32hi \
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{ 0, 1, 2, 3, 4, 5, 6, 7, \
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8, 9, 10, 11, 12, 13, 14, 15, \
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34, 53, 41, 55, 57, 43, 36, 39, \
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62, 48, 50, 51, 49, 44, 60, 37 }
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#define PERM_CONST_CONCAT0_v32hi_l \
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{ 32, 33, 34, 35, 36, 37, 38, 39, \
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40, 41, 42, 43, 44, 45, 46, 47, \
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31, 0, 29, 2, 27, 4, 25, 6, 23, \
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8, 21, 10, 19, 12, 17, 14 }
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#define PERM_CONST_CONCAT0_v16hi \
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{ 0, 1, 2, 3, 4, 5, 6, 7, \
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21, 26, 17, 31, 24, 22, 30, 19 }
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#define PERM_CONST_CONCAT0_v16hi_l \
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{ 16, 17, 18, 19, 20, 21, 22, 23, \
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15, 0, 13, 2, 11, 4, 9, 6 }
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#define PERM_CONST_CONCAT0_v8hi \
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{ 0, 1, 2, 3, 9, 11, 14, 12 }
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#define PERM_CONST_CONCAT0_v8hi_l \
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{ 8, 9, 10, 11, 3, 5, 1, 7 }
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#define PERM_CONST_CONCAT0(type) \
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PERM_CONST_CONCAT0_##type
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#define PERM_CONST_CONCAT0_L(type) \
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PERM_CONST_CONCAT0_##type##_l
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#define SHUFFLE_CONST_CONCAT0(type, itype) \
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type foo_##type##shuffle_const_concat0 (type a) \
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{ \
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return __builtin_shuffle (a, (type) {0}, \
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(itype) PERM_CONST_CONCAT0 (itype)); \
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} \
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type foo_##type##shuffle_const_concat0_l (type a) \
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{ \
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return __builtin_shuffle ((type) {0}, a, \
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(itype) PERM_CONST_CONCAT0_L (itype)); \
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}
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SHUFFLE_CONST_CONCAT0 (v32hf, v32hi)
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SHUFFLE_CONST_CONCAT0 (v16hf, v16hi)
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SHUFFLE_CONST_CONCAT0 (v8hf, v8hi)
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