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RISC-V/testsuite: Add branchless cases for FP NE cond-add operation

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Verify, for the generic floating-point NE conditional-add operation,
that if-conversion triggers via `noce_try_addcc' at `-mbranch-cost=3'
setting, which makes branchless code sequences emitted by if-conversion
cheaper than their original branched equivalents, and that extraneous
instructions such as SNEZ, etc. are not present in output.

The reason to XFAIL the SImode test for RV64 targets is GCC thinks it
has to sign-extend addends, which causes if-conversion to give up.

	gcc/testsuite/
	* gcc.target/riscv/adddifne.c: New test.
	* gcc.target/riscv/addsifne.c: New test.
This commit is contained in:
Maciej W. Rozycki 2023-11-22 01:18:31 +00:00
parent 23207facbb
commit 6300e672c8
2 changed files with 52 additions and 0 deletions
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26
gcc/testsuite/gcc.target/riscv/adddifne.c Normal file
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/* { dg-do compile } */
/* { dg-require-effective-target rv64 } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
typedef int __attribute__ ((mode (DI))) int_t;
int_t
adddifne (double w, double x, int_t y, int_t z)
{
return w != x ? y + z : y;
}
/* Expect branchless assembly like:
feq.d a5,fa0,fa1
addi a5,a5,-1
and a5,a5,a1
add a0,a5,a0
*/
/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */

26
gcc/testsuite/gcc.target/riscv/addsifne.c Normal file
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/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
typedef int __attribute__ ((mode (SI))) int_t;
int_t
addsifne (double w, double x, int_t y, int_t z)
{
return w != x ? y + z : y;
}
/* Expect branchless assembly like:
feq.d a5,fa0,fa1
addi[w] a5,a5,-1
and a5,a5,a1
add[w] a0,a5,a0
*/
/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" { xfail rv64 } } } */