From 6300e672c86236720952227bc4fd6a6dc4eeb55a Mon Sep 17 00:00:00 2001
From: "Maciej W. Rozycki" <macro@embecosm.com>
Date: Wed, 22 Nov 2023 01:18:31 +0000
Subject: [PATCH] RISC-V/testsuite: Add branchless cases for FP NE cond-add
 operation

Verify, for the generic floating-point NE conditional-add operation,
that if-conversion triggers via `noce_try_addcc' at `-mbranch-cost=3'
setting, which makes branchless code sequences emitted by if-conversion
cheaper than their original branched equivalents, and that extraneous
instructions such as SNEZ, etc. are not present in output.

The reason to XFAIL the SImode test for RV64 targets is GCC thinks it
has to sign-extend addends, which causes if-conversion to give up.

	gcc/testsuite/
	* gcc.target/riscv/adddifne.c: New test.
	* gcc.target/riscv/addsifne.c: New test.
---
 gcc/testsuite/gcc.target/riscv/adddifne.c | 26 +++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsifne.c | 26 +++++++++++++++++++++++
 2 files changed, 52 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/adddifne.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/addsifne.c

diff --git a/gcc/testsuite/gcc.target/riscv/adddifne.c b/gcc/testsuite/gcc.target/riscv/adddifne.c
new file mode 100644
index 00000000000..58fcb401ef7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddifne.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddifne (double w, double x, int_t y, int_t z)
+{
+  return w != x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	addi	a5,a5,-1
+	and	a5,a5,a1
+	add	a0,a5,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsifne.c b/gcc/testsuite/gcc.target/riscv/addsifne.c
new file mode 100644
index 00000000000..9875d62b43b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsifne.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsifne (double w, double x, int_t y, int_t z)
+{
+  return w != x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	addi[w]	a5,a5,-1
+	and	a5,a5,a1
+	add[w]	a0,a5,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" { xfail rv64 } } } */