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Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.

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gcc/

	* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
	"yes" where needed.

From-SVN: r211899
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James Greenhalgh 2014-06-23 16:00:02 +00:00 • committed by James Greenhalgh
parent 82bb92454f
commit 0379033b63
2 changed files with 7 additions and 1 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2014-06-23 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
"yes" where needed.
2014-06-23 Alan Modra <amodra@gmail.com> 2014-06-23 Alan Modra <amodra@gmail.com>
PR bootstrap/61583 PR bootstrap/61583

3
gcc/config/aarch64/aarch64.md
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@ -1167,7 +1167,8 @@
add\\t%w0, %w1, %w2 add\\t%w0, %w1, %w2
add\\t%0.2s, %1.2s, %2.2s add\\t%0.2s, %1.2s, %2.2s
sub\\t%w0, %w1, #%n2" sub\\t%w0, %w1, #%n2"
[(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")] [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")
(set_attr "simd" "*,*,yes,*")]
) )
;; zero_extend version of above ;; zero_extend version of above