From 0379033b6388ad245e8926766929012c27b6f20a Mon Sep 17 00:00:00 2001
From: James Greenhalgh <james.greenhalgh@arm.com>
Date: Mon, 23 Jun 2014 16:00:02 +0000
Subject: [PATCH] Re: [AArch64] Implement ADD in vector registers for 32-bit
 scalar values.

gcc/

	* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
	"yes" where needed.

From-SVN: r211899
---
 gcc/ChangeLog                 | 5 +++++
 gcc/config/aarch64/aarch64.md | 3 ++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7979ff98fea..32917ef5e4a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2014-06-23  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
+	"yes" where needed.
+
 2014-06-23  Alan Modra  <amodra@gmail.com>
 
 	PR bootstrap/61583
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 5f5b4ff89b6..8705ee9d189 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1167,7 +1167,8 @@
   add\\t%w0, %w1, %w2
   add\\t%0.2s, %1.2s, %2.2s
   sub\\t%w0, %w1, #%n2"
-  [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")]
+  [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")
+   (set_attr "simd" "*,*,yes,*")]
 )
 
 ;; zero_extend version of above