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Author SHA1 Message Date
Hu, Lin1
8170af78e1 Support Intel USER_MSR 
This patches aims to support Intel USER_MSR. In addition to the usual
support, this patch includes encoding and decoding support for MAP7 and
immediate numbers as the last operand (ATT style).

gas/ChangeLog:

	* NEWS: Support Intel USER_MSR.
	* config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit
	mode.
	(build_vex_prefix): Add VEXMAP7.
	(md_assemble): Handling the imm32 of USER_MSR.
	(match_template): Handling the unusual immediate.
	* doc/c-i386.texi: Document .user_msr.
	* testsuite/gas/i386/i386.exp: Run USER_MSR tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/user_msr-inval.l: New test.
	* testsuite/gas/i386/user_msr-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-user_msr-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-user_msr-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-user_msr.d: Ditto.
	* testsuite/gas/i386/x86-64-user_msr.s: Ditto.

opcodes/ChangeLog:
	* i386-dis.c (struct instr_info): Add a new attribute
	has_skipped_modrm.
	(Gq): New.
	(Rq): Ditto.
	(q_mm_mode): Ditto.
	(Nq): Change mode from q_mode to q_mm_mode.
	(VEX_LEN_TABLE):
	(get_valid_dis386): Add VEX_MAP7 in VEX prefix.
	and handle the map7_f8 for save space.
	(OP_Skip_MODRM): Set has_skipped_modrm.
	(OP_E): Skip codep++ when has skipped modrm byte.
	(OP_R): Support q_mode and q_mm_mode.
	(REG_VEX_MAP7_F8_L_0_W_0): New.
	(PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto.
	(X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto.
	(VEX_LEN_MAP7_F8): Ditto.
	(VEX_W_MAP7_F8_L_0): Ditto.
	(MOD_0F38F8): Ditto.
	(PREFIX_0F38F8_M_0): Ditto.
	(PREFIX_0F38F8_M_1_X86_64): Ditto.
	(X86_64_0F38F8_M_1): Ditto.
	(PREFIX_0F38F8): Remove.
	(prefix_table): Add PREFIX_0F38F8_M_1_X86_64.
	Remove PREFIX_0F38F8.
	(reg_table): Add REG_VEX_MAP7_F8_L_0_W_0,
	PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64.
	(x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1,
	X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1.
	(vex_table): Add VEX_MAP7.
	(vex_len_table): Add VEX_LEN_MAP7_F8,
	VEX_W_MAP7_F8_L_0.
	(mod_table): New entry for USER_MSR and
	add MOD_0F38F8.
	* i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and
	CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (SPACE_VEXMAP7): New.
	(CPU_USER_MSR_FLAGS): Ditoo.
	(CPU_ANY_USER_MSR_FLAGS): Ditto.
	(i386_cpu_flags): Add cpuuser_msr.
	* i386-opc.tbl: Add USER_MSR instructions.
	* i386-tbl.h: Regenerated.
 2023-10-31 16:24:41 +08:00
Saurabh Jha
0515a7b643 aarch64: Enable Cortex-X4 CPU 2023-10-05 11:09:45 +01:00
Claudiu Zissulescu
f14cd06ba4 Revert "arc: Update NEWS files" 
This reverts commit a47d304b12.
 2023-09-25 17:01:47 +03:00
Claudiu Zissulescu
a47d304b12 arc: Update NEWS files 
Add ARCv3 support in NEWS files.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
 2023-09-25 11:33:12 +03:00
Jan Beulich
4fc85f37dc x86: support AVX10.1 vector size restrictions 
Recognize "/<number>" suffixes on both -march=+avx10.1 and the
corresponding .arch directive, setting an upper bound on the vector size
that insns may use. Such a restriction can be reset by setting a new base
architecture, by using a suffix-less form, by disabling AVX10, or by
enabling any other VEX/EVEX-based vector extension.

While for most insns we can suppress their use with too wide operands
via registers becoming unavailable (or in Intel syntax memory operand
size specifiers not being recognized), mask register insns have to have
their minimum required vector size specified in a new attribute. (Of
course this new attribute could also be used on other insns.)

Note that .insn continues to be permitted to emit EVEX{512,256} (and
VEX256 ones) encodings regardless of vector size restrictions in place.
Of course these can't be expressed using zmm (or ymm) operands then,
but need using the EVEX.512.* forms (broadcast forms may be usable right
now, but this may go away so shouldn't be relied upon). This is why no
assertions should be added to build_{e,}vex_prefix().
 2023-09-14 08:43:45 +02:00
Paul Iannetta
6e712424f5 kvx: New port. 2023-08-16 14:22:54 +01:00
Richard Ball
7d6a2e34ee aarch64: Enable Cortex-A720 CPU 
This patch adds support for the Cortex-A720 CPU to binutils.

bfd/ChangeLog:

	* cpu-aarch64.c: Add Cortex-A720.

gas/ChangeLog:

	* NEWS: Update docs.
	* config/tc-aarch64.c: Add Cortex-A720.
	* doc/c-aarch64.texi: Update docs.
	* testsuite/gas/aarch64/cpu-cortex-a720.d: New test.
 2023-08-16 14:08:09 +01:00
Richard Ball
67bed49ec8 aarch64: Enable Cortex-A520 CPU 
This patch adds support for the Cortex-A520 CPU to gas.

No regressions on aarch64-none-elf.

gas/ChangeLog:

	* NEWS: Update docs.
	* config/tc-aarch64.c: Add Cortex-A520.
	* doc/c-aarch64.texi: Update docs.
 2023-08-10 15:12:23 +01:00
Sam James
b5c37946cc Revert "2.41 Release sources" 
This reverts commit 675b9d612c.

See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
 2023-08-02 12:06:23 +01:00
Nick Clifton
675b9d612c 2.41 Release sources 2023-08-02 09:23:36 +01:00
Hu, Lin1
cd2908958a Support Intel PBNDKB 
gas/ChangeLog:

	* NEWS: Support Intel PBNDKB.
	* config/tc-i386.c: Add pbndkb.
	* doc/c-i386.texi: Document .pbndkb.
	* testsuite/gas/i386/i386.exp: Add PBNDKB tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/pbndkb-inval.l: New test.
	* testsuite/gas/i386/pbndkb-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-pbndkb.d: Ditto.
	* testsuite/gas/i386/x86-64-pbndkb.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New.
	(X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto.
	(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7.
	(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0.
	(rm_table): New entry for pbndkb.
	* i386-gen.c (cpu_flag): Add PBNDKB.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuPBNDKB): New.
	(i386_cpu_flags): Add cpupbndkb.
	* i386-opc.tbl: Add PBNDKB instructions.
	* i386-tbl.h: Regenerated.
 2023-07-27 20:52:52 +08:00
Haochen Jiang
2bced1684b Support Intel SM4 
gas/ChangeLog:

	* NEWS: Support Intel SM4.
	* config/tc-i386.c: Add sm4.
	* doc/c-i386.texi: Document .sm4.
	* testsuite/gas/i386/i386.exp: Run SM4 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sm4-intel.d: Add SM4 tests.
	* testsuite/gas/i386/sm4.d: Ditto.
	* testsuite/gas/i386/sm4.s: Ditto.
	* testsuite/gas/i386/x86-64-sm4-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sm4.d: Ditto.
	* testsuite/gas/i386/x86-64-sm4.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (prefix_table): Add SM4 instructions.
	* i386-gen.c (isa_dependencies): Add SM4.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSM4): New.
	(i386_cpu_flags): Add cpusm4.
	* i386-opc.tbl: Add SM4 instructions.
	* i386-tbl.h: Regenerated.
 2023-07-27 20:52:46 +08:00
Haochen Jiang
c55ba32b7a Support Intel SM3 
gas/ChangeLog:

	* NEWS: Support Intel SM3.
	* config/tc-i386.c: Add sm3.
	* doc/c-i386.texi: Document .sm3.
	* testsuite/gas/i386/i386.exp: Run sm3 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sm3-intel.d: New test.
	* testsuite/gas/i386/sm3.d: Ditto.
	* testsuite/gas/i386/sm3.s: Ditto.
	* testsuite/gas/i386/x86-64-sm3-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sm3.d: Ditto.
	* testsuite/gas/i386/x86-64-sm3.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_VEX_0F38DA_W_0): New.
	(VEX_LEN_0F38DA_W_0_P_0): Ditto.
	(VEX_LEN_0F38DA_W_0_P_2): Ditto.
	(VEX_LEN_0F3ADE_W_0): Ditto.
	(VEX_W_0F38DA): Ditto.
	(VEX_W_0F3ADE): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38DA_W_0.
	(vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0,
	VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0.
	(vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE.
	* i386-gen.c (isa_dependencies): Add SM3.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSM3): New.
	(i386_cpu_flags): Add cpusm3.
	* i386-opc.tbl: Add SM3 instructions.
	* i386-tbl.h: Regenerated.
 2023-07-27 20:52:25 +08:00
Haochen Jiang
3ac2eb9481 Support Intel SHA512 
gas/ChangeLog:

	* NEWS: Support Intel SHA512.
	* config/tc-i386.c: Add sha512.
	* doc/c-i386.texi: Document .sha512.
	* testsuite/gas/i386/disassem.d: Add SHA512 tests.
	* testsuite/gas/i386/disassem.s: Ditto.
	* testsuite/gas/i386/i386.exp: Run SHA512 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sha512-intel.d: New test.
	* testsuite/gas/i386/sha512-inval.l: Ditto.
	* testsuite/gas/i386/sha512-inval.s: Ditto.
	* testsuite/gas/i386/sha512.d: Ditto.
	* testsuite/gas/i386/sha512.s: Ditto.
	* testsuite/gas/i386/x86-64-sha512-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sha512-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-sha512-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-sha512.d: Ditto.
	* testsuite/gas/i386/x86-64-sha512.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (Rxmmq): New.
	(Rymm): Ditto.
	(PREFIX_VEX_0F38CB): Ditto.
	(PREFIX_VEX_0F38CC): Ditto.
	(PREFIX_VEX_0F38CD): Ditto.
	(VEX_LEN_0F38CB_P_3_W_0): Ditto.
	(VEX_LEN_0F38CC_P_3_W_0): Ditto.
	(VEX_LEN_0F38CD_P_3_W_0): Ditto.
	(VEX_W_0F38CB_P_3): Ditto.
	(VEX_W_0F38CC_P_3): Ditto.
	(VEX_W_0F38CD_P_3): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC,
	PREFIX_VEX_0F38CD.
	(vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0,
	VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0.
	(vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3.
	* i386-gen.c (isa_dependencies): Add SHA512.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSHA512): New.
	(i386_cpu_flags): Add cpusha512.
	* i386-opc.tbl: Add SHA512 instructions.
	* i386-tbl.h: Regenerated.
 2023-07-27 20:52:17 +08:00
konglin1
3fde5f6e7d Support Intel AVX-VNNI-INT16 
gas/ChangeLog:

	* NEWS: Support Intel AVX-VNNI-INT16.
	* config/tc-i386.c: Add avx_vnni_int16.
	* doc/c-i386.texi: Document avx_vnni_int16.
	* testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/avx-vnni-int16-intel.d: New test.
	* testsuite/gas/i386/avx-vnni-int16.d: New test.
	* testsuite/gas/i386/avx-vnni-int16.s: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_VEX_0F38D2_W_0): New.
	(PREFIX_VEX_0F38D3_W_0): Ditto.
	(VEX_W_0F38D2_P_0): Ditto.
	(VEX_W_0F38D2_P_1): Ditto.
	(VEX_W_0F38D2_P_2): Ditto.
	(VEX_W_0F38D3_P_0): Ditto.
	(VEX_W_0F38D3_P_1): Ditto.
	(VEX_W_0F38D3_P_2): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38D2_W_0 and
	PREFIX_VEX_0F38D3_W_0.
	(vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3.
	(vex_w_table): Ditto.
	* i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16.
	(cpu_flag): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h: (CpuAVX_VNNI_INT16): New.
	* i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions.
	* i386-tbl.h: Regenerated.
 2023-07-27 20:51:20 +08:00
Nick Clifton
d501d38488 Add markers for the 2.41 branch 2023-07-03 11:12:15 +01:00
WANG Xuerui
3863e5e491 gas: NEWS: Announce LoongArch changes in the 2.41 cycle 
gas/ChangeLog:

	* NEWS: Mention LoongArch changes for 2.41.

Signed-off-by: WANG Xuerui <git@xen0n.name>
 2023-07-03 09:00:51 +08:00
Zhang, Jun
c88ed92f0c Support Intel FRED LKGS 
gas/ChangeLog:

	* NEWS: Support Intel FRED LKGS.
	* config/tc-i386.c: Add fred lkgs
	* doc/c-i386.texi: Document .fred, .lkgs.
	* testsuite/gas/i386/i386.exp: Add FRED LKGS tests
	* testsuite/gas/i386/x86-64-fred-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-fred.d: Ditto.
	* testsuite/gas/i386/x86-64-fred.s: Ditto.
	* testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-lkgs.d: Ditto.
	* testsuite/gas/i386/x86-64-lkgs.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c: New entry for fred, lkgs.
	* i386-gen.c: Add CPU_FRED CPU_LKGS.
	* i386-init.h : Regenerated.
	* i386-mnem.h : Regenerated.
	* i386-opc.h: Add fred, lkgs.
	* i386-opc.tbl: Add FRED, LKGS instructions.
	* i386-tbl.h: Regenerated.
 2023-05-23 14:43:23 +08:00
liuhongt
cbf25f4705 Revert "Support Intel FRED LKGS" 
This reverts commit e5a497fe38.
 2023-05-23 14:42:20 +08:00
Zhang, Jun
e5a497fe38 Support Intel FRED LKGS 
gas/ChangeLog:

        * NEWS: Support Intel FRED LKGS.
        * config/tc-i386.c: Add fred lkgs
        * doc/c-i386.texi: Document .fred, .lkgs.
        * testsuite/gas/i386/i386.exp: Add FRED LKGS tests
        * testsuite/gas/i386/x86-64-fred-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-fred.d: Ditto.
        * testsuite/gas/i386/x86-64-fred.s: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto.
        * testsuite/gas/i386/x86-64-lkgs.d: Ditto.
        * testsuite/gas/i386/x86-64-lkgs.s: Ditto.

opcodes/ChangeLog:

        * i386-dis.c: New entry for fred, lkgs.
        * i386-gen.c: Add CPU_FRED CPU_LKGS.
        * i386-init.h : Regenerated.
        * i386-mnem.h : Regenerated.
        * i386-opc.h: Add fred, lkgs.
        * i386-opc.tbl: Add FRED, LKGS instructions.
        * i386-tbl.h: Regenerated.
 2023-05-23 13:50:40 +08:00
Haochen Jiang
d100d8c1f3 Support Intel AMX-COMPLEX 
gas/ChangeLog:

	* NEWS: Support Intel AMX-COMPLEX.
	* config/tc-i386.c: Add amx_complex.
	* doc/c-i386.texi: Document .amx_complex.
	* testsuite/gas/i386/i386.exp: Run AMX-COMPLEX tests.
	* testsuite/gas/i386/amx-complex-inval.l: New test.
	* testsuite/gas/i386/amx-complex-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex-bad.d: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex-bad.s: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex.d: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (MOD_VEX_0F386C_X86_64_W_0): New.
	(PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0): Ditto.
	(X86_64_VEX_0F386C): Ditto.
	(VEX_LEN_0F386C_X86_64_W_0_M_1): Ditto.
	(VEX_W_0F386C_X86_64): Ditto.
	(mod_table): Add MOD_VEX_0F386C_X86_64_W_0.
	(prefix_table): Add PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0.
	(x86_64_table): Add X86_64_VEX_0F386C.
	(vex_len_table): Add VEX_LEN_0F386C_X86_64_W_0_M_1.
	(vex_w_table): Add VEX_W_0F386C_X86_64.
	* i386-gen.c (cpu_flag_init): Add CPU_AMX_COMPLEX_FLAGS and
	CPU_ANY_AMX_COMPLEX_FLAGS.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuAMX_COMPLEX): New.
	(i386_cpu_flags): Add cpuamx_complex.
	* i386-opc.tbl: Add AMX-COMPLEX instructions.
	* i386-tbl.h: Regenerated.
 2023-04-07 05:47:01 +00:00
Jan Beulich
695a8c347a x86: document .insn 
... and mention its introduction in NEWS.
 2023-03-31 08:25:24 +02:00
Richard Sandiford
60336e1965 aarch64: Add +sme2 
This patch adds bare-bones support for +sme2.  Later patches
fill in the rest.
 2023-03-30 11:09:10 +01:00
Alan Modra
d87bef3a7b Update year range in copyright notice of binutils files 
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
 2023-01-01 21:50:11 +10:30
Nick Clifton
a72b07181d Add markers for 2.40 branch 2022-12-31 12:05:28 +00:00
Christoph Müllner
01804a098d RISC-V: Add T-Head Int vendor extension 
This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
 2022-11-17 16:43:55 +08:00
Christoph Müllner
4a3bc79bf4 RISC-V: Add T-Head Fmv vendor extension 
This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
 2022-11-17 16:43:49 +08:00
Indu Bhagat
b2cb03d5c3 gas/NEWS: add text about new command line option and SFrame support 
ChangeLog:

	* gas/NEWS: Add SFrame related news.
 2022-11-15 15:50:05 -08:00
Srinath Parvathaneni
cafdb713d8 arm: Add support for Cortex-X1C CPU. 
This patch adds support for Cortex-X1C CPU in Arm.

bfd/ChangeLog:

2022-11-09  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

        * cpu-arm.c (processors): Add Cortex-X1C CPU entry.

gas/ChangeLog:

2022-11-09  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

        * NEWS: Update docs.
        * config/tc-arm.c (arm_cpus): Add cortex-x1c to -mcpu.
        * doc/c-arm.texi: Update docs.
        * testsuite/gas/arm/cpu-cortex-x1c.d: New test.
 2022-11-14 13:56:05 +00:00
Kong Lingling
b06311adb4 Support Intel RAO-INT 
gas/ChangeLog:

	* NEWS: Support Intel RAO-INT.
	* config/tc-i386.c: Add raoint.
	* doc/c-i386.texi: Document .raoint.
	* testsuite/gas/i386/i386.exp: Run RAO_INT tests.
	* testsuite/gas/i386/raoint-intel.d: New test.
	* testsuite/gas/i386/raoint.d: Ditto.
	* testsuite/gas/i386/raoint.s: Ditto.
	* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-raoint.d: Ditto.
	* testsuite/gas/i386/x86-64-raoint.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_0F38FC): New.
	(prefix_table): Add PREFIX_0F38FC.
	* i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and
	CPU_ANY_RAO_INT_FLAGS.
	* i386-init.h: Regenerated.
	* i386-opc.h: (CpuRAO_INT): New.
	(i386_cpu_flags): Add cpuraoint.
	* i386-opc.tbl: Add RAO_INT instructions.
	* i386-tbl.h: Regenerated.
 2022-11-08 10:24:59 +08:00
konglin1
01d8ce742c Support Intel AVX-NE-CONVERT 
gas/ChangeLog:

	* NEWS: Support Intel AVX-NE-CONVERT.
	* config/tc-i386.c: Add avx_ne_convert.
	* doc/c-i386.texi: Document .avx_ne_convert.
	* testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests.
	* testsuite/gas/i386/avx-ne-convert-intel.d: New test.
	* testsuite/gas/i386/avx-ne-convert.d: Ditto.
	* testsuite/gas/i386/avx-ne-convert.s: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (Mw): New.
	(PREFIX_VEX_0F3872): Ditto.
	(PREFIX_VEX_0F38B0_W_0): Ditto.
	(PREFIX_VEX_0F38B1_W_0): Ditto.
	(VEX_W_0F3872_P_1): Ditto.
	(VEX_W_0F38B0): Ditto.
	(VEX_W_0F38B1): Ditto.
	(prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0,
	PREFIX_VEX_0F38B1_W_0.
	(vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and
	CPU_ANY_AVX_NE_CONVERT_FLAGS.
	(cpu_flags): Add CpuAVX_NE_CONVERT.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX_NE CONVERT): New.
	(i386_cpu_flags): Add cpuavx_ne_convert.
	* i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions.
	* i386-tbl.h: Regenerated.
 2022-11-04 11:42:17 +08:00
Hu, Lin1
2188d6ea4f Support Intel MSRLIST 
gas/ChangeLog:

	* NEWS: Support Intel MSRLIST.
	* config/tc-i386.c: Add msrlist.
	* doc/c-i386.texi: Document .msrlist.
	* testsuite/gas/i386/i386.exp: Add MSRLIST tests.
	* testsuite/gas/i386/msrlist-inval.l: New test.
	* testsuite/gas/i386/msrlist-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-msrlist.d: Ditto.
	* testsuite/gas/i386/x86-64-msrlist.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New.
	(X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto.
	(prefix_table): New entry for msrlist.
	(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1
	and X86_64_0F01_REG_0_MOD_3_RM_6_P_3.
	* i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS
	and CPU_ANY_MSRLIST_FLAGS.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuMSRLIST): New.
	(i386_cpu_flags): Add cpumsrlist.
	* i386-opc.tbl: Add MSRLIST instructions.
	* i386-tbl.h: Regenerated.
 2022-11-02 09:19:26 +08:00
Hu, Lin1
941f083324 Support Intel WRMSRNS 
gas/ChangeLog:

        * NEWS: Support Intel WRMSRNS.
        * config/tc-i386.c: Add wrmsrns.
        * doc/c-i386.texi: Document .wrmsrns.
        * testsuite/gas/i386/i386.exp: Add WRMSRNS tests.
        * testsuite/gas/i386/wrmsrns-intel.d: New test.
        * testsuite/gas/i386/wrmsrns.d: Ditto.
        * testsuite/gas/i386/wrmsrns.s: Ditto.
        * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New.
	(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6.
	(rm_table): New entry for wrmsrns.
	* i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS
	and CPU_ANY_WRMSRNS_FLAGS.
	(cpu_flags): Add CpuWRMSRNS.
        * i386-init.h: Regenerated.
        * i386-opc.h (CpuWRMSRNS): New.
	(i386_cpu_flags): Add cpuwrmsrns.
        * i386-opc.tbl: Add WRMSRNS instructions.
        * i386-tbl.h: Regenerated.
 2022-11-02 09:19:24 +08:00
Haochen Jiang
a93e323427 Support Intel CMPccXADD 
gas/ChangeLog:

	* NEWS: Support Intel CMPccXADD.
	* config/tc-i386.c: Add cmpccxadd.
	(build_modrm_byte): Add operations for Vex.VVVV reg
	on operand 0 while have memory operand.
	* doc/c-i386.texi: Document .cmpccxadd.
	* testsuite/gas/i386/i386.exp: Run CMPccXADD tests.
	* testsuite/gas/i386/cmpccxadd-inval.s: New test.
	* testsuite/gas/i386/cmpccxadd-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto.
	* testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (Mdq): New.
	(X86_64_VEX_0F38E0): Ditto.
	(X86_64_VEX_0F38E1): Ditto.
	(X86_64_VEX_0F38E2): Ditto.
	(X86_64_VEX_0F38E3): Ditto.
	(X86_64_VEX_0F38E4): Ditto.
	(X86_64_VEX_0F38E5): Ditto.
	(X86_64_VEX_0F38E6): Ditto.
	(X86_64_VEX_0F38E7): Ditto.
	(X86_64_VEX_0F38E8): Ditto.
	(X86_64_VEX_0F38E9): Ditto.
	(X86_64_VEX_0F38EA): Ditto.
	(X86_64_VEX_0F38EB): Ditto.
	(X86_64_VEX_0F38EC): Ditto.
	(X86_64_VEX_0F38ED): Ditto.
	(X86_64_VEX_0F38EE): Ditto.
	(X86_64_VEX_0F38EF): Ditto.
	(x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1,
	X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4,
	X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7,
	X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA,
	X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED,
	X86_64_VEX_0F38EE, X86_64_VEX_0F38EF.
	* i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and
	CPU_ANY_CMPCCXADD_FLAGS.
	(cpu_flags): Add CpuCMPCCXADD.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuCMPCCXADD): New.
	(i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0.
	* i386-opc.tbl: Add Intel CMPccXADD instructions.
	* i386-tbl.h: Regenerated.
 2022-11-02 09:19:22 +08:00
Cui,Lili
23ae61ad89 Support Intel AVX-VNNI-INT8 
gas/
        * NEWS: Support Intel AVX-VNNI-INT8.
	* config/tc-i386.c: Add avx_vnni_int8.
	* doc/c-i386.texi: Document avx_vnni_int8.
	* testsuite/gas/i386/avx-vnni-int8-intel.d: New file.
	* testsuite/gas/i386/avx-vnni-int8.d: Likewise.
	* testsuite/gas/i386/avx-vnni-int8.s: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests.

opcodes/
	* i386-dis.c: (PREFIX_VEX_0F3850) New.
	(PREFIX_VEX_0F3851): Likewise.
	(VEX_W_0F3850_P_0): Likewise.
	(VEX_W_0F3850_P_1): Likewise.
	(VEX_W_0F3850_P_2): Likewise.
	(VEX_W_0F3850_P_3): Likewise.
	(VEX_W_0F3851_P_0): Likewise.
	(VEX_W_0F3851_P_1): Likewise.
	(VEX_W_0F3851_P_2): Likewise.
	(VEX_W_0F3851_P_3): Likewise.
	(VEX_W_0F3850): Delete.
	(VEX_W_0F3851): Likewise.
	(prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851.
	(vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851,
	delete VEX_W_0F3850 and VEX_W_0F3851.
	(vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2
	VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2
	and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851.
	* i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS
	and CPU_ANY_AVX_VNNI_INT8_FLAGS.
	(cpu_flags): Add CpuAVX_VNNI_INT8.
	* i386-opc.h (CpuAVX_VNNI_INT8): New.
	* i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2022-11-02 09:19:20 +08:00
Hongyu Wang
4321af3e4d Support Intel AVX-IFMA 
x86: Support Intel AVX-IFMA

Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is
cleared by default.  Without {vex} pseudo prefix, Intel IFMA instructions
are encoded with EVEX prefix.  {vex} pseudo prefix will turn on VEX
encoding for Intel IFMA instructions.

gas/

	* NEWS: Support Intel AVX-IFMA.
	* config/tc-i386.c (cpu_arch): Add avx_ifma.
	* doc/c-i386.texi: Document .avx_ifma.
	* testsuite/gas/i386/avx-ifma.d: New file.
	* testsuite/gas/i386/avx-ifma-intel.d: Likewise.
	* testsuite/gas/i386/avx-ifma.s: Likewise.
	* testsuite/gas/i386/x86-64-avx-ifma.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-ifma.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run AVX IFMA tests.

opcodes/

	* i386-dis.c (PREFIX_VEX_0F38B4): New.
	(PREFIX_VEX_0F38B5): Likewise.
	(VEX_W_0F38B4_P_2): Likewise.
	(VEX_W_0F38B5_P_2): Likewise.
	(prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5.
	(vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2.
	* i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA.
	* i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in
	CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and
	CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS.
	(cpu_flags): Add CpuAVX_IFMA.
	* i386-opc.h (CpuAVX_IFMA): New.
	(i386_cpu_flags): Add cpuavx_ifma.
	* i386-opc.tbl: Add Intel AVX IFMA instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
 2022-11-02 09:19:20 +08:00
Cui, Lili
ef07be453e Support Intel PREFETCHI 
gas/ChangeLog:

	* NEWS: Add support for Intel PREFETCHI instruction.
	* config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches.
	(md_assemble): Add warning for illegal input of PREFETCHI.
	* doc/c-i386.texi: Document .prefetchi.
	* testsuite/gas/i386/i386.exp: Run PREFETCHI tests.
	* testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI.
	* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetch.d: New test.
	* testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise..
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.s: Likewise.

opcodes/ChangeLog:

	* i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7
	(x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0.
	(mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7.
	(prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and
	PREFIX_0F18_REG_7_MOD_0_X86_64.
	(PREFETCHI_Fixup): New.
	* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS.
	(cpu_flags): Add CpuPREFETCHI.
	* i386-opc.h (CpuPREFETCHI): New.
	(i386_cpu_flags): Add cpuprefetchi.
	* i386-opc.tbl: Add Intel PREFETCHI instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2022-10-31 21:15:29 +08:00
Palmer Dabbelt
f262d2df3a
gas: NEWS: Note support for RISC-V Zawrs 
This has been supported since eb668e5003 ("RISC-V: Add Zawrs ISA
extension support").
 2022-10-28 15:45:48 -07:00
Palmer Dabbelt
d846c35eaf
gas: NEWS: Add a missing newline 2022-10-28 15:45:48 -07:00
Cui,Lili
68830fbae9 Support Intel AMX-FP16 
gas/

	* NEWS: Add support for Intel AMX-FP16 instruction.
	* config/tc-i386.c: Add amx_fp16.
	* doc/c-i386.texi: Document .amx_fp16.
	* testsuite/gas/i386/i386.exp: Add AMX-FP16 tests.
	* testsuite/gas/i386/x86-64-amx-fp16-intel.d: New test.
	* testsuite/gas/i386/x86-64-amx-fp16.d: Likewise.
	* testsuite/gas/i386/x86-64-amx-fp16.s: Likewise.
	* testsuite/gas/i386/x86-64-amx-fp16-bad.d: Likewise.
	* testsuite/gas/i386/x86-64-amx-fp16-bad.s: Likewise.

opcodes/

	* i386-dis.c (MOD_VEX_0F385C_X86_64_P_3_W_0): New.
	(VEX_LEN_0F385C_X86_64_P_3_W_0_M_0): Likewise.
	(VEX_W_0F385C_X86_64_P_3): Likewise.
	(prefix_table): Add VEX_W_0F385C_X86_64_P_3.
	(vex_len_table): Add VEX_LEN_0F385C_X86_64_P_3_W_0_M_0.
	(vex_w_table): Add VEX_W_0F385C_X86_64_P_3.
	(mod_table): Add MOD_VEX_0F385C_X86_64_P_3_W_0.
	* i386-gen.c (cpu_flag_init): Add AMX-FP16_FLAGS.
	(CPU_ANY_AMX_TILE_FLAGS): Add CpuAMX_FP16.
	(cpu_flags): Add CpuAMX-FP16.
	* i386-opc.h (enum): Add CpuAMX-FP16.
	(i386_cpu_flags): Add cpuamx_fp16.
	* i386-opc.tbl: Add Intel AMX-FP16 instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2022-10-21 10:49:19 +08:00
Martin Liska
b0c295e1b8 add --enable-default-compressed-debug-sections-algorithm configure option 
ChangeLog:

	* configure.ac: Add --enable-default-compressed-debug-sections-algorithm.
	* configure: Regenerate.

gas/ChangeLog:

	* NEWS: Document the new option.
	* as.c (flag_compress_debug): Set default algorithm based
	on the configure option.
	* configure.ac: Add --enable-default-compressed-debug-sections-algorithm.
	* configure: Regenerate.
	* config.in: Likewise.

ld/ChangeLog:

	* NEWS: Document the new option.
	* configure.ac: Add --enable-default-compressed-debug-sections-algorithm.
	* configure: Regenerate.
	* config.in: Likewise.
	* ldmain.c: Set default algorithm based
	on the configure option.
 2022-10-11 14:15:04 +02:00
Palmer Dabbelt
27e602128b
gas: NEWS: Mention the T-Head extensions that were recently added 2022-10-04 13:32:33 -07:00
Fangrui Song
2cac01e3ff binutils, gdb: support zstd compressed debug sections 
PR29397 PR29563: Add new configure option --with-zstd which defaults to
auto.  If pkgconfig/libzstd.pc is found, define HAVE_ZSTD and support
zstd compressed debug sections for most tools.

* bfd: for addr2line, objdump --dwarf, gdb, etc
* gas: support --compress-debug-sections=zstd
* ld: support ELFCOMPRESS_ZSTD input and --compress-debug-sections=zstd
* objcopy: support ELFCOMPRESS_ZSTD input for
  --decompress-debug-sections and --compress-debug-sections=zstd
* gdb: support ELFCOMPRESS_ZSTD input.  The bfd change references zstd
  symbols, so gdb has to link against -lzstd in this patch.

If zstd is not supported, ELFCOMPRESS_ZSTD input triggers an error.  We
can avoid HAVE_ZSTD if binutils-gdb imports zstd/ like zlib/, but this
is too heavyweight, so don't do it for now.

```
% ld/ld-new a.o
ld/ld-new: a.o: section .debug_abbrev is compressed with zstd, but BFD is not built with zstd support
...

% ld/ld-new a.o --compress-debug-sections=zstd
ld/ld-new: --compress-debug-sections=zstd: ld is not built with zstd support

% binutils/objcopy --compress-debug-sections=zstd a.o b.o
binutils/objcopy: --compress-debug-sections=zstd: binutils is not built with zstd support

% binutils/objcopy b.o --decompress-debug-sections
binutils/objcopy: zstd.o: section .debug_abbrev is compressed with zstd, but BFD is not built with zstd support
...
```
 2022-09-26 19:50:13 -07:00
Palmer Dabbelt
5a3ca6e319 gas: NEWS: Add the RISC-V features for 2.39 2022-08-25 16:10:13 +08:00
Palmer Dabbelt
6b60a1ec10 gas: NEWS: Add the RISC-V features for 2.38 2022-08-25 16:10:10 +08:00
Palmer Dabbelt
157a088c1e gas: NEWS: Add the RISC-V features for 2.37 2022-08-25 16:10:07 +08:00
Palmer Dabbelt
c17cf68c8c gas: NEWS: Add the RISC-V features for 2.36 2022-08-25 16:10:05 +08:00
Palmer Dabbelt
4362996c0e gas: NEWS: Add the RISC-V features for 2.35 2022-08-25 16:10:02 +08:00
Palmer Dabbelt
64411043fd gas: NEWS: Add the RISC-V features for 2.31 2022-08-25 16:09:59 +08:00
Nick Clifton
0bd0932314 Add markers for 2.39 branch 2022-07-08 10:41:07 +01:00