Commit graph

10205 commits

Author SHA1 Message Date
Jan Beulich
22c3694052 x86: fold certain AVX2 templates into their AVX counterparts
Like for AVX512VL we can make the handling of operand sizes a little
more flexible to allow reducing the number of templates we have.
2022-03-18 10:54:53 +01:00
Tsukasa OI
41d6ac5da6 RISC-V: Cache management instructions
This commit adds 'Zicbom' / 'Zicboz' instructions.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
	new instruction classes.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
	MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
	MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add cache-block management
	instructions.
2022-03-18 15:32:22 +08:00
Tsukasa OI
3b374308d3 RISC-V: Prefetch hint instructions and operand set
This commit adds 'Zicbop' hint instructions.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
	new instruction class.

gas/ChangeLog:

	* config/tc-riscv.c (riscv_ip): Add handling for new operand
	type 'f' (32-byte aligned pseudo S-type immediate for prefetch
	hints).
	(validate_riscv_insn): Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
	MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
	MASK_PREFETCH_W): New macros.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	class INSN_CLASS_ZICBOP.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add handling for new operand
	type.
	* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
2022-03-18 15:32:16 +08:00
Alan Modra
5fac3f02ed PR28977 tc-i386.c internal error in parse_register
PR 28977
	* config/tc-i386.c (parse_register): Handle X_op not O_register
	as for a non-reg_section symbol.  Simplify array bounds check.
2022-03-18 17:24:13 +10:30
Alan Modra
9e2c342294 Tidy gas current_frame before exit
Releases some obstack memory on an error path.

	* cond.c (cond_finish_check): Call cond_exit_macro.
2022-03-18 16:37:36 +10:30
Alan Modra
ecc263d676 ubsan: logical_input_line signed integer overflow
To avoid a completely useless fuzzing ubsan "bug" report, I decided to
make logical_input_line unsigned.

	* input-scrub.c (logical_input_line): Make unsigned.
	(struct input_save): Here too.
	(input_scrub_reinit, input_scrub_close, bump_line_counters),
	(as_where): Adjust to suit.
2022-03-18 16:37:36 +10:30
Alan Modra
4c5f3d0c9e asan: use of uninitialized value in buffer_and_nest
More occurences of the same as commit d12b8d620c.

	* macro.c (buffer_and_nest): Sanity check length in buffer
	before calling strncasecmp.
2022-03-17 21:32:44 +10:30
Alan Modra
0d1064face asan: buffer overflows after calling ignore_rest_of_line
operand() is not a place that should be calling ignore_rest_of_line.
ignore_rest_of_line shouldn't increment input_line_pointer if already
at buffer limit.

	* expr.c (operand): Don't call ignore_rest_of_line.
	* read.c (s_mri_common): Likewise.
	(ignore_rest_of_line): Don't increment input_line_pointer if
	already at buffer_limit.
2022-03-17 21:32:44 +10:30
Jan Beulich
ed971d9fa6 x86: don't accept base architectures as extensions
The -march= intentions are quite clear: A base architecture may be
followed by any number of extensions. Accepting a base architecture in
place of an extension will at best result in confusion, as the first of
the two (or more) items specified simply would not take effect, due to
being overridden by the later one(s).
2022-03-17 11:05:56 +01:00
Jan Beulich
b1f8a900fd x86: add another IAMCU testcase
Now that {L,K}1OM support is gone, and with it the brokenness in
check_cpu_arch_compatible(), put in place a test making sure that only
extensions can be enabled via .arch for IAMCU, and that the base
architecture cannot be changed.
2022-03-17 11:03:22 +01:00
Jan Beulich
c085ab00c7 x86: drop L1OM/K1OM support from gas
This was only rudimentary support anyway; none of the sub-architecture
specific insns were ever supported.
2022-03-17 11:02:42 +01:00
Jan Beulich
648d04db39 x86: assorted IAMCU CPU checking fixes
The checks done by check_cpu_arch_compatible() were halfway sensible
only at the time where only L1OM support was there. The purpose,
however, has always been to prevent bad uses of .arch (turning off the
base CPU "feature" flag) while at the same time permitting extensions to
be enabled / disabled. In order to achieve this (and to prevent
regressions when L1OM and K1OM support are removed)
- set CpuIAMCU in CPU_IAMCU_FLAGS,
- adjust the IAMCU check in the function itself (the other two similarly
  broken checks aren't adjusted as they're slated to be removed anyway),
- avoid calling the function for extentions (which would never have the
  base "feature" flag set),
- add a new testcase actually exercising ".arch iamcu" (which would also
  regress with the planned removal).
2022-03-17 11:01:38 +01:00
Alan Modra
dc3ff92676 Delete PowerPC macro insn support
Let's hope this stays dead, but it's here as a patch separate from
those that removed use of powerpc_macros just in case it needs to be
resurrected.

include/
	* opcode/ppc.h (struct powerpc_macro): Delete declaration.
	(powerpc_macros, powerpc_num_macros): Likewise..
opcodes/
	* ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete.
gas/
	* config/tc-ppc.c (ppc_macro): Delete function.
	(ppc_macro_hash): Delete.
	(ppc_setup_opcodes, md_assemble): Delete macro support.
2022-03-16 10:08:46 +10:30
Alan Modra
51ba92c795 PowerPC VLE extended instructions in powerpc_macros
This moves VLE insn out of the macro table.  "e_slwi" and "e_srwi"
already exist in vle_opcodes as distinct instructions rather than
encodings of e_rlwinm.

opcodes/
	* ppc-opc.c (vle_opcodes): Typo fix e_rlwinm operand.
	Add "e_inslwi", "e_insrwi", "e_rotlwi", "e_rotrwi", "e_clrlwi",
	"e_clrrwi", "e_extlwi", "e_extrwi", and "e_clrlslwi".
	(powerpc_macros): Delete same.  Delete "e_slwi" and "e_srwi" too.
gas/
	* testsuite/gas/ppc/vle-simple-5.d: Update.
2022-03-16 10:07:02 +10:30
Alan Modra
f304c63d24 PowerPC32 extended instructions in powerpc_macros
As for PowerPC64, move instructions to the main opcode table.

opcodes/
	* ppc-opc.c (insert_crwn, extract_crwn, insert_elwn, extract_elwn),
	(insert_erwn, extract_erwn, insert_erwb, extract_erwb),
	(insert_cslwn, extract_cslwb, insert_ilwb, extract_ilwn),
	(insert_irwb, extract_irwn, insert_rrwn, extract_rrwn),
	(insert_slwn, extract_slwn, insert_srwn, extract_srwn): New functions.
	(CRWn, ELWn, ERWn, ERWb, CSLWb, CSLWn, ILWn, ILWb, IRWn, IRWb),
	(RRWn, SLWn, SRWn): Define and add powerpc_operands entries.
	(MMB_MASK, MME_MASK, MSHMB_MASK): Define.
	(powerpc_opcodes): Add "inslwi", "insrwi", "rotrwi", "clrrwi",
	"slwi", "srwi", "extlwi", "extrwi", "sli", "sri" and corresponding
	record (ie. dot suffix) forms.
	(powerpc_macros): Delete same.
gas/
	* testsuite/gas/ppc/476.d: Update.
	* testsuite/gas/ppc/simpshft.d: Update.
2022-03-16 10:05:37 +10:30
Alan Modra
42952a9605 PowerPC64 extended instructions in powerpc_macros
The extended instructions implemented in powerpc_macros aren't used by
the disassembler.  That means instructions like "sldi r3,r3,2" appear
in disassembly as "rldicr r3,r3,2,61", which is annoying since many
other extended instructions are shown.

Note that some of the instructions moved out of the macro table to the
opcode table won't appear in disassembly, because they are aliases
rather than a subset of the underlying raw instruction.  If enabled,
rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all
occurrences of rotldi, rldicl, rldicr, rldic and rldimi.  (Or many
occurrences in the case of clrlsldi if n <= b was added to the extract
functions.)

The patch also fixes a small bug in opcode sanity checking.

include/
	* opcode/ppc.h (PPC_OPSHIFT_SH6): Define.
opcodes/
	* ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn),
	(insert_crdn, extract_crdn, insert_rrdn, extract_rrdn),
	(insert_sldn, extract_sldn, insert_srdn, extract_srdn),
	(insert_erdb, extract_erdb, insert_csldn, extract_csldb),
	(insert_irdb, extract_irdn): New functions.
	(ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb):
	Define and add associated powerpc_operands entries.
	(powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi",
	"sldi", "extldi", "clrlsldi", "insrdi" and corresponding record
	(ie. dot suffix) forms.
	(powerpc_macros): Delete same from here.
gas/
	* config/tc-ppc.c (insn_validate): Don't modify value passed
	to operand->insert for PPC_OPERAND_PLUS1 when calculating mask.
	Handle PPC_OPSHIFT_SH6.
	* testsuite/gas/ppc/prefix-reloc.d: Update.
	* testsuite/gas/ppc/simpshft.d: Update.
ld/
	* testsuite/ld-powerpc/elfv2so.d: Update.
	* testsuite/ld-powerpc/notoc.d: Update.
	* testsuite/ld-powerpc/notoc3.d: Update.
	* testsuite/ld-powerpc/tlsdesc2.d: Update.
	* testsuite/ld-powerpc/tlsget.d: Update.
	* testsuite/ld-powerpc/tlsget2.d: Update.
	* testsuite/ld-powerpc/tlsopt5.d: Update.
	* testsuite/ld-powerpc/tlsopt6.d: Update.
2022-03-16 09:59:07 +10:30
Alan Modra
fb0e49d8e0 Constant fold view increment expressions
The idea here is to replace expressions like v + 1 + 1 + 1 with v + 3.

	* dwarf2dbg.c (set_or_check_view): Remove useless assertion.
	Resolve multiple view increments.
	* testsuite/gas/elf/dwarf2-18.d: Don't xfail mep.
2022-03-09 15:50:34 +10:30
Alan Modra
4afc889439 Reduce duplicated symbol_clone_if_forward_ref work
* symbol.c (struct symbol_flags): Add forward_resolved.
	(symbol_entry_find): Update needle initialisation.
	(symbol_clone_if_forward_ref): Do no work when forward_resolved
	is already set.  Set forward_resolved.
2022-03-09 14:10:00 +10:30
Jan Beulich
7919e5667c RISC-V: make .insn actually work for 64-bit insns
Presently in this case, due to an undefined behavior shift, at least
with x86 cross builds I'm observing:

Error: value conflicts with instruction length `8,0x0000003f'

Eliminate the UB and extend the respective testcase.
2022-03-04 13:37:59 +01:00
Jan Beulich
6a778a2100 x86: drop redundant x86-64-code16-2 test
The code16-2 test is already meaningless enough as a gas test, identical
to this one, and is run uniformly for all ELF targets anyway.
2022-03-04 13:37:30 +01:00
Patrick O'Neill
e4028336b1 RISC-V: PR28733, add missing extension info to 'unrecognized opcode' error
Currently we report errors as "unrecognized opcode `fence.i'" when the
opcode isn't part of the selected extensions.
This patch expands that error message to include the missing extension
information. For example, now the error message would be "unrecognized
opcode `fence.i', extension `zifencei' required".
If the opcode is not a part of any extension, the error message reverts
to "unrecognized opcode `<op statement>'".

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

bfd/
	pr 28733
	* elfxx-riscv.c (riscv_multi_subset_supports_ext): New function,
	used to return the extension string for each INSN_CLASS_*.
	* elfxx-riscv.h: Added extern riscv_multi_subset_supports_ext.
gas/
	pr 28733
	* config/tc-riscv.c (struct riscv_ip_error): New structure,
	contains information about errors that occur within the riscv_ip.
	(riscv_ip): Use struct riscv_ip_error to report more detailed errors.
	* testsuite/gas/riscv/c-fld-fsd-fail.l: Updated.
	* testsuite/gas/riscv/march-imply-i2p1-01.: Likewise.
2022-02-23 19:45:52 +08:00
Patrick O'Neill
df0a549ebd RISC-V: PR28733, add missing extension info to 'invalid CSR' error
Currently we report errors as "invalid CSR 'fscr' for the current ISA"
when the instruction isn't valid.

This patch expands that error message to include the missing extension
information. For example, now the error message would be "invalid CSR
'fscr' for the current ISA, CSR 'fscr' needs 'f' extension".

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

gas/
	pr 28733
	* config/tc-riscv.c (riscv_csr_address): Report more details
	when the CSR is invalid.
	* testsuite/gas/riscv/csr-version-1p10.l: Updated detailed errors.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
2022-02-23 19:08:19 +08:00
Alan Modra
cebc89b932 binutils 2.38 vs. ppc32 linux kernel
Commit b25f942e18 made .machine more strict.  Weaken it again.

	* config/tc-ppc.c (ppc_machine): Treat an early .machine specially,
	keeping sticky options to work around gcc bugs.
2022-02-23 19:23:09 +10:30
Nelson Chu
9cbed90ee6 RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.
* Removed N extension CSRs,
ustatus, uie, utvec, uscratch, uepc, ucause, utval and uip.

* Removed two supervisor CSRs,
sedeleg and sideleg.

* Changed debug CSR address of scontext from 0x7aa to 0x5a8.  We cannot support
different versions of debug specs for now, so only supporting the latest one is
the only way to move forward.

* Added debug CSRs,
mscontext (0x7aa), mcontrol6 (0x7a1, tdata1) and tmexttrigger ((0x7a1, tdata1).

* Regarded hcontext as a debug CSR.

include/
	* opcode/riscv-opc.h: Updated CSRs to privileged spec v1.12 and
	debug spec v1.0.
gas/
	* testsuite/gas/riscv/csr.s: Updated CSRs to privileged spec v1.12
	and debug spec v1.0.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
2022-02-23 14:54:34 +08:00
Tsukasa OI
f4ce10b14f RISC-V: Add Privileged Architecture 1.12 CSRs
This commit adds,

* Most of CSRs as listed in the Privileged Architecture,
version 1.12 (except scontext and mscontext).

* Testcases for most CSRs added on the Privileged
Architecture, version 1.12 (except moved "scontext" and
new "mscontext").

include/ChangeLog:

	* opcode/riscv-opc.h (CSR_SENVCFG, CSR_MCONFIGPTR, CSR_MENVCFG,
	CSR_MSTATUSH, CSR_MENVCFGH, CSR_MTINST, CSR_MTVAL2, CSR_MSECCFG,
	CSR_MSECCFGH, CSR_PMPCFG4, CSR_PMPCFG5, CSR_PMPCFG6,
	CSR_PMPCFG7, CSR_PMPCFG8, CSR_PMPCFG9, CSR_PMPCFG10,
	CSR_PMPCFG11, CSR_PMPCFG12, CSR_PMPCFG13, CSR_PMPCFG14,
	CSR_PMPCFG15, CSR_PMPADDR16, CSR_PMPADDR17, CSR_PMPADDR18,
	CSR_PMPADDR19, CSR_PMPADDR20, CSR_PMPADDR21, CSR_PMPADDR22,
	CSR_PMPADDR23, CSR_PMPADDR24, CSR_PMPADDR25, CSR_PMPADDR26,
	CSR_PMPADDR27, CSR_PMPADDR28, CSR_PMPADDR29, CSR_PMPADDR30,
	CSR_PMPADDR31, CSR_PMPADDR32, CSR_PMPADDR33, CSR_PMPADDR34,
	CSR_PMPADDR35, CSR_PMPADDR36, CSR_PMPADDR37, CSR_PMPADDR38,
	CSR_PMPADDR39, CSR_PMPADDR40, CSR_PMPADDR41, CSR_PMPADDR42,
	CSR_PMPADDR43, CSR_PMPADDR44, CSR_PMPADDR45, CSR_PMPADDR46,
	CSR_PMPADDR47, CSR_PMPADDR48, CSR_PMPADDR49, CSR_PMPADDR50,
	CSR_PMPADDR51, CSR_PMPADDR52, CSR_PMPADDR53, CSR_PMPADDR54,
	CSR_PMPADDR55, CSR_PMPADDR56, CSR_PMPADDR57, CSR_PMPADDR58,
	CSR_PMPADDR59, CSR_PMPADDR60, CSR_PMPADDR61, CSR_PMPADDR62,
	CSR_PMPADDR63): New CSR macros.

gas/ChangeLog:

	* testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr.s: Add new CSRs.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
2022-02-23 14:45:44 +08:00
Tsukasa OI
7379729c7d RISC-V: Reorganize testcases for CFI directives
This commit reorganizes and adds some CSRs to csr-dw-regnums.[sd] to
make it test the same CSRs as csr.s.

gas/ChangeLog:

	* testsuite/gas/riscv/csr-dw-regnums.s: Reorganize and add
	defined CSRs tested in csr.s.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
2022-02-23 14:45:34 +08:00
Alan Modra
19f7966ede gas local label and dollar label handling
Much of the gas source and older BFD source use "long" for function
parameters and variables, when other types would be more appropriate.
This patch fixes one of those cases.  Dollar labels and numeric local
labels do not need large numbers.  Small positive itegers are usually
all that is required.  Due to allowing longs, it was possible for
fb_label_name and dollar_label_name to overflow their buffers.

	* symbols.c: Delete unnecessary forward declarations.
	(dollar_labels, dollar_label_instances): Use unsigned int.
	(dollar_label_defined, dollar_label_instance): Likewise.
	(define_dollar_label): Likewise.
	(fb_low_counter, fb_labels, fb_label_instances): Likewise.
	(fb_label_instance_inc, fb_label_instance): Likewise.
	(fb_label_count, fb_label_max): Make them size_t.
	(dollar_label_name, fb_label_name): Rewrite using sprintf.
	* symbols.h (dollar_label_defined): Update prototype.
	(define_dollar_label, dollar_label_name): Likewise.
	(fb_label_instance_inc, fb_label_name): Likewise.
	* config/bfin-lex.l (yylex): Remove unnecessary casts.
	* expr.c (integer_constant): Likewise.
	* read.c (read_a_source_file): Limit numeric label range to int.
2022-02-16 22:05:24 +10:30
Alan Modra
969f6a63c0 ubsan: s_app_line integer overflow
There are quite a few ubsan warnings in gas.  This one disappears with
a code tidy.

	* read.c (s_app_line): Rename 'l' to 'linenum'.  Avoid ubsan
	warning.
2022-02-16 22:05:24 +10:30
Alan Modra
d12b8d620c asan : use of uninitialized value in buffer_and_nest
* macro.c (buffer_and_nest): Don't read past end of string buffer.
2022-02-16 19:15:40 +10:30
Richard Sandiford
b4b0dcfd03 gas/doc: Fix "a true results" typo 2022-02-11 15:08:46 +00:00
Nick Clifton
2f49159cfb Updated French translation for the gas sub-directory. 2022-01-28 12:16:03 +00:00
Mike Frysinger
9a84a44d5d gas: drop old cygnus install hack
This was needed when gas was using the automake cygnus option, but
this was removed years ago by Simon in d0ac1c4488
("Bump to autoconf 2.69 and automake 1.15.1").  So delete it here.
The info pages are already & still installed by default w/out it.
2022-01-24 19:58:33 -05:00
Nick Clifton
5fe73d4624 Update Bulgarian, French, Romaniam and Ukranian translation for some of the sub-directories 2022-01-24 14:22:49 +00:00
H.J. Lu
ad69b6b861 Regenerate Makefile.in files with automake 1.15.1
Regenerate Makefile.in files with the unmodified automake 1.15.1 to
remove

runstatedir = @runstatedir@

bfd/

	* Makefile.in: Regenerate.

binutils/

	* Makefile.in: Regenerate.

gas/

	* Makefile.in: Regenerate.

gold/

	* Makefile.in: Regenerate.
	* testsuite/Makefile.in: Likewise.

gprof/

	* Makefile.in: Regenerate.

ld/

	* Makefile.in: Regenerate.

opcodes/

	* Makefile.in: Regenerate.
2022-01-23 06:59:20 -08:00
H.J. Lu
31b0378d53 Regenerate configure files with autoconf 2.69
Regenerate configure files with the unmodified autoconf 2.69 to remove

  --runstatedir=DIR       modifiable per-process data [LOCALSTATEDIR/run]

bfd/

	* configure: Regenerate.

binutils/

	* configure: Regenerate.

gas/

	* configure: Regenerate.

gold/

	* configure: Regenerate.

gprof/

	* configure: Regenerate.

ld/

	* configure: Regenerate.

opcodes/

	* configure: Regenerate.
2022-01-23 05:27:01 -08:00
Nick Clifton
f908e960c5 Change version number to 2.38.50 and regenerate files 2022-01-22 12:39:28 +00:00
Nick Clifton
a74e1cb344 Add markers for 2.38 branch 2022-01-22 12:08:55 +00:00
Lifang Xia
cb2562f553 RISC-V: create new frag after alignment.
PR 28793:

The alignment may be removed in linker. We need to create new frag after
alignment to prevent the assembler from computing static offsets.

gas/
	* config/tc-riscv.c (riscv_frag_align_code): Create new frag.
2022-01-22 17:20:18 +08:00
Mike Frysinger
ec7194506d drop old unused stamp-h.in file
This was needed by ancient versions of automake, but that hasn't been
the case since at least automake-1.5, so punt this from the tree.
2022-01-21 03:11:47 -05:00
Nick Clifton
6c037fdbf0 Update the config.guess and config.sub files from the master repository and regenerate files. 2022-01-17 16:21:22 +00:00
Sergey Belyashov
1adce770ea Fix Z80 assembly failure.
PR 28762
	* app.c (do_scrub_chars): Correct handling when the symbol is not 'af'.
2022-01-17 13:00:17 +00:00
Alan Modra
1ffce3f87d Re: gas: add visibility support using GNU syntax on XCOFF
tc-ppc.c: In function 'ppc_comm':
tc-ppc.c:4560:40: error: 'visibility' may be used uninitialized in this function [-Werror=maybe-uninitialized]

With that fixed we hit lots of segfaults in the ld testsuite.

	PR 22085
bfd/
	* xcofflink.c (xcoff_link_input_bfd): Don't segfault on NULL
	sym_hash.
gas/
	* config/tc-ppc.c (ppc_comm): Init visibility.
2022-01-13 16:50:15 +10:30
Clément Chigot
09d4578fd9 gas: add visibility support using GNU syntax on XCOFF
In order to ease port of GNU assembly code and especially ld testsuite,
this patch allows XCOFF to accept the usual GNU syntax for visibility.

PR 22085

gas/ChangeLog:

	* config/tc-ppc.c (ppc_GNU_visibility): New function.
	* testsuite/gas/ppc/aix.exp: Add new tests.
	* testsuite/gas/ppc/xcoff-visibility-2-32.d: New test.
	* testsuite/gas/ppc/xcoff-visibility-2-64.d: New test.
	* testsuite/gas/ppc/xcoff-visibility-2.s: New test.
2022-01-12 09:08:17 +01:00
Clément Chigot
add588a8ef gas: add visibility support for XCOFF
XCOFF assembly defines the visibility using an additional argument
on several pseudo-ops: .globl, .weak, .extern and .comm.
This implies that .globl and .weak syntax is different than the
usual GNU syntax. But we want to provide compatibility with AIX
assembler, especially because GCC is generating the visibility
using this XCOFF syntax.

PR 22085

bfd/ChangeLog:

        * coffcode.h (coff_write_object_contents): Change XCOFF header
        vstamp field to 2.
        * coffgen.c (coff_print_symbol): Increase the size for n_type.

gas/ChangeLog:

        * config/tc-ppc.c (ppc_xcoff_get_visibility): New function.
        (ppc_globl): New function.
        (ppc_weak): New function.
        (ppc_comm): Add visibility field support.
        (ppc_extern): Likewise.
        * testsuite/gas/all/cofftag.d: Adjust to new n_type size
        providing by objdump.
        * testsuite/gas/ppc/test1xcoff32.d: Likewise.
        * testsuite/gas/ppc/aix.exp: Add new tests.
        * testsuite/gas/ppc/xcoff-visibility-1-32.d: New test.
        * testsuite/gas/ppc/xcoff-visibility-1-64.d: New test.
        * testsuite/gas/ppc/xcoff-visibility-1.s: New test.

include/ChangeLog:

        * coff/internal.h (SYM_V_INTERNAL, SYM_V_HIDDEN,
        SYM_V_PROTECTED, SYM_V_EXPORTED, SYM_V_MASK): New defines.
        * coff/xcoff.h (struct xcoff_link_hash_entry): Add visibility
        field.

ld/ChangeLog:

        * testsuite/ld-pe/pr19803.d: Adjust to new n_type size
        providing by objdump.
2022-01-12 09:08:11 +01:00
Hans-Peter Nilsson
c4f5871457 objdump, readelf: Emit "CU:" format only when wide output is requested
As pre-approved by Alan in
https://sourceware.org/pipermail/binutils/2021-September/118019.html
and I believe people have run into getting testsuite failures for
test-environments with "long" directory names, at least once more
since that time.  Enough.  I grepped the gas, binutils and ld
testsuites for "CU:" to catch target-specific occurrences, but I
noticed none.  I chose to remove "CU:" on the objdump tests instead of
changing options to get the wide format, so as to keep the name of the
test consistent with actual options; but added it to the readelf
options for the gas test as I believe the "CU:" format is preferable.

Tested for cris-elf and native x86_64-pc-linux-gnu.

binutils:
	* dwarf.c (display_debug_lines_decoded): Don't check the
	string length of the directory, instead emit the "CU: dir/name"
	format only if wide output is requested.
	* testsuite/binutils-all/dw5.W, testsuite/binutils-all/objdump.WL:
	Adjust accordingly.

gas:
	* testsuite/gas/elf/dwarf-5-loc0.d: Add -W to readelf options.
2022-01-12 05:51:25 +01:00
Jan Beulich
d02f2788c3 gas/doc: mention quoted symbol names 2022-01-11 15:43:34 +01:00
Clément Chigot
3c5038247c XCOFF: add support for TLS relocations on hidden symbols
This patch adds support for TLS relocation targeting C_HIDEXT symbols.
In gas, TLS relocations, except R_TLSM and R_TLMSL, must keep the value
of their target symbol.
In ld, it simply ensures that internal TLS symbols are added to the
linker hash table for xcoff_reloc_type_tls.

It also improves the tests made by both.

bfd/ChangeLog:

	* coff-rs6000.c (xcoff_howto_table): Fix name of R_TLSML.
	(xcoff_reloc_type_tls): Replace the error when h is NULL by
	an assert.
	(xcoff_complain_overflow_unsigned_func): Adjust comments.
	* coff64-rs6000.c (xcoff64_howto_table): Fix name of R_TLSML.
	* xcofflink.c (xcoff_link_add_symbols_to_hash_table): New
	function.
	(xcoff_link_add_symbols): Add C_HIDEXT TLS symbols to the linker
	hash table.

gas/ChangeLog:

	* config/tc-ppc.c (md_apply_fix): Enable support for TLS
	relocation over internal symbols.
	* testsuite/gas/ppc/aix.exp: Replace xcoff-tlms by xcoff-tls.
	* testsuite/gas/ppc/xcoff-tlsm-32.d: Removed.
	* testsuite/gas/ppc/xcoff-tlsm-64.d: Removed.
	* testsuite/gas/ppc/xcoff-tlsm.s: Removed.
	* testsuite/gas/ppc/xcoff-tls-32.d: New test.
	* testsuite/gas/ppc/xcoff-tls-64.d: New test.
	* testsuite/gas/ppc/xcoff-tls.s: New test.

ld/ChangeLog:

	* testsuite/ld-powerpc/aix52.exp: Improve aix-tls-reloc test.
	* testsuite/ld-powerpc/aix-tls-reloc.s: Likewise.
	* testsuite/ld-powerpc/aix-tls-reloc-32.d: Removed.
	* testsuite/ld-powerpc/aix-tls-reloc-64.d: Removed.
	* testsuite/ld-powerpc/aix-tls-reloc-32.dd: New test.
	* testsuite/ld-powerpc/aix-tls-reloc-32.dt: New test.
	* testsuite/ld-powerpc/aix-tls-reloc-64.dd: New test.
	* testsuite/ld-powerpc/aix-tls-reloc-64.dt: New test.
2022-01-10 09:14:57 +01:00
Philipp Tomsich
9fba072133 RISC-V: update docs to reflect privileged spec v1.9 has been dropped
After commit d8af286fff ("RISC-V: Drop the privileged spec v1.9
support.") has removed support for privileged spec v1.9, this removes
it from the documentation.

References: d8af286fff ("RISC-V: Drop the privileged spec v1.9 support.")

gas/ChangeLog:

	* configure: Regenerate.
	* configure.ac: Remove reference to priv spec 1.9.
	* po/fr.po: Same.
	* po/ru.po: Same.
	* po/uk.po: Same.
2022-01-07 23:41:25 +01:00
Philipp Tomsich
86d39e66f5 RISC-V: update docs for -mpriv-spec/--with-priv-spec for 1.12
While support for the privileged spec was added in a63375ac33
("RISC-V: Hypervisor ext: support Privileged Spec 1.12"), the
documentation has not been updated.  Add 1.12 to the relevant
documentation.

References: a63375ac33 ("RISC-V: Hypervisor ext: support Privileged Spec 1.12")

gas/ChangeLog:

	* config/tc-riscv.c: Add 1.12 to the usage message.
	* configure: Regenerate.
	* configure.ac: Add 1.12 to the help/usage message.
	* po/fr.po: Same.
	* po/ru.po: Same.
	* po/uk.po: Same.
2022-01-07 23:40:30 +01:00
Nelson Chu
aed44286ef RISC-V: Updated the default ISA spec to 20191213.
Update the default ISA spec from 2.2 to 20191213 will change the default
version of i from 2.0 to 2.1.  Since zicsr and zifencei are separated
from i 2.1, users need to add them in the architecture string if they need
fence.i and csr instructions.  Besides, we also allow old ISA spec can
recognize zicsr and zifencei, but we won't output them since they are
already included in the i extension when i's version is less than 2.1.

bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
	recognize zicsr and zifencei.
gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
	* testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
	* testsuite/gas/riscv/option-arch-03.s: Likewise.
ld/
	* testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei
	into Tag_RISCV_arch since it is added implied when i's version is
	larger than 2.1.
2022-01-07 18:48:29 +08:00