Add the MT ASE instruction operand types and encodings to the microMIPS
opcode table and enable the assembly of these instructions in GAS from
MIPSr2 onwards. Update the binutils and GAS testsuites accordingly.
References:
"MIPS Architecture for Programmers, Volume IV-f: The MIPS MT Module for
the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number:
MD00768, Revision 1.12, July 16, 2013
Co-Authored-By: Maciej W. Rozycki <macro@redhat.com>
(cherry picked from commit 08e6af1bac935c0820c51a9e6a52294b4ae4d832)
We have an ISA check for the '--trap' command-line option that reports
its incompatibility with the MIPS I architecture. It doesn't prevent
trap instructions from being enabled though, so when attempt is made to
emit one in an expansion of one of the division or multiplication macros
an assertion failure triggers:
.../gas/testsuite/gas/mips/brtr-opt.s: Assembler messages:
.../gas/testsuite/gas/mips/brtr-opt.s:3: Error: trap exception not supported at ISA 1
.../gas/testsuite/gas/mips/brtr-opt.s:9: Warning: divide by zero
.../gas/testsuite/gas/mips/brtr-opt.s:9: Internal error in macro_build at .../gas/config/tc-mips.c:9064.
Please report this bug.
The same assertion failure triggers without an earlier error message
when the initial ISA is compatible with the '--trap', however at the
time an attempt is made to emit a trap instruction from a division or
multiplication macro the ISA has been changed by a '.set' pseudo-op to
an incompatible one.
With the way the situations are mishandled it seems unlikely that anyone
relies on the current semantics and a sane approach is to decide on the
fly according to the currently selected ISA as to whether to emit trap
or breakpoint instructions in the case where '--trap' has been used.
Change our code to do so then and clarify that in the manual, which is
not explicit about how '--trap' is handled with a changing ISA. Mention
the change in NEWS too since it's a applies to a user option.
MIPSr6 removes condition trap instructions with imm, so we expand
the instruction like "tne $2,IMM" to
li $at,IMM
tne $2,$at
While if IMM is 0, we can use
tne $2,$zero
only.
Catching this at configure time would be nicer, but we'd need to exactly
match mips_parse_cpu in configure.ac and keep it all in sync.
PR 23877
* config/tc-mips.c (mips_after_parse_args): Don't assert that
mips_parse_cpu returns non-NULL, call as_fatal with an informative
message instead.
Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
No caller outside of obj-elf.c cares about the parameter - drop it by
introducing an obj-elf.c-internal wrapper.
While adding the new function parameter, take the opportunity and change
the adjacent boolean one to "bool".
The Allegrex CPU supports bit rotation instructions as described in the
MIPS32 release 2 CPU (even though it is a MIPS-2 based CPU).
Signed-off-by: David Guillen Fandos <david@davidgf.net>
The Allegrex CPU was created by Sony Interactive Entertainment to power
their portable console, the PlayStation Portable.
The pspdev organization maintains all sorts of tools to create software
for said device including documentation.
Signed-off-by: David Guillen Fandos <david@davidgf.net>
When configure with triples mipsisa[32,64]rN[el,], the march value
is pinned to a fix value if not given explicitly. for example
1) mipsisa32r6-linux-gnu -n32 xx.s will complains that:
-march=mips32r6 is not compatible with the selected ABI
2) mipsisa64r2el-linux-gnu -o32 generates objects with 64bit CPU:
ELF 32-bit LSB relocatable, MIPS, MIPS64 rel2 version 1 (SYSV)
They are not good default behaviors: Let's alter the CPU info
Since we are using these triples as a regular linux distributions,
let's alter march according to ABI.
Testing for NULL in pic_need_relax fixes the other call to this
function in md_estimate_size_before_relax.
PR 28955
* config/tc-mips.c (mips_frob_file): Move NULL sym test to..
(pic_need_relax): ..here.
-mfix-looongson3-llsc may add sync instructions not needed on some
asm code with lots of debug info.
PR: 30153
* gas/config/tc-mips.c(fix_loongson3_llsc): clear logistic.
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
These two macros print either a 16 digit hex number or an 8 digit
hex number. Unfortunately they depend on both target and host, which
means that the output for 32-bit targets may be either 8 or 16 hex
digits.
Replace them in most cases with code that prints a bfd_vma using
PRIx64. In some cases, deliberately lose the leading zeros.
This change some output, notably in base/offset fields of m68k
disassembly which I think looks better that way, and in error
messages. I've kept leading zeros in symbol dumps (objdump -t)
and in PE header dumps.
bfd/
* bfd-in.h (fprintf_vma, sprintf_vma, printf_vma): Delete.
* bfd-in2.h: Regenerate.
* bfd.c (bfd_sprintf_vma): Don't use sprintf_vma.
(bfd_fprintf_vma): Don't use fprintf_vma.
* coff-rs6000.c (xcoff_reloc_type_tls): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(xcoff_ppc_relocate_section): Likewise.
* cofflink.c (_bfd_coff_write_global_sym): Likewise.
* mmo.c (mmo_write_symbols_and_terminator): Likewise.
* srec.c (srec_write_symbols): Likewise.
* elf32-xtensa.c (print_r_reloc): Similarly for fprintf_vma.
* pei-x86_64.c (pex64_dump_xdata): Likewise.
(pex64_bfd_print_pdata_section): Likewise.
* som.c (som_print_symbol): Likewise.
* ecoff.c (_bfd_ecoff_print_symbol): Use bfd_fprintf_vma.
opcodes/
* dis-buf.c (perror_memory, generic_print_address): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* i386-dis.c (print_operand_value, print_displacement): Likewise.
* m68k-dis.c (print_base, print_indexed): Likewise.
* ns32k-dis.c (print_insn_arg): Likewise.
* ia64-gen.c (_opcode_int64_low, _opcode_int64_high): Delete.
(opcode_fprintf_vma): Delete.
(print_main_table): Use PRIx64 to print opcode.
binutils/
* od-macho.c: Replace all uses of printf_vma with bfd_printf_vma.
* objcopy.c (copy_object): Don't use sprintf_vma. Instead use
PRIx64 to print bfd_vma values.
(copy_main): Likewise.
* readelf.c (CHECK_ENTSIZE_VALUES): Likewise.
(dynamic_section_mips_val): Likewise.
(print_vma): Don't use printf_vma. Instead use PRIx64 to print
bfd_vma values.
(dump_ia64_vms_dynamic_fixups): Likewise.
(process_version_sections): Likewise.
* rddbg.c (stab_context): Likewise.
gas/
* config/tc-i386.c (offset_in_range): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(md_assemble): Likewise.
* config/tc-mips.c (load_register, macro): Likewise.
* messages.c (as_internal_value_out_of_range): Likewise.
* read.c (emit_expr_with_reloc): Likewise.
* config/tc-ia64.c (note_register_values): Don't use fprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(print_dependency): Likewise.
* listing.c (list_symbol_table): Use bfd_sprintf_vma.
* symbols.c (print_symbol_value_1): Use %p to print pointers.
(print_binary): Likewise.
(print_expr_1): Use PRIx64 to print bfd_vma values.
* write.c (print_fixup): Use %p to print pointers. Don't use
fprintf_vma.
* testsuite/gas/all/overflow.l: Update expected output.
* testsuite/gas/m68k/mcf-mov3q.d: Likewise.
* testsuite/gas/m68k/operands.d: Likewise.
* testsuite/gas/s12z/truncated.d: Likewise.
ld/
* deffilep.y (def_file_print): Don't use fprintf_vma. Instead
use PRIx64 to print bfd_vma values.
* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* emultempl/pe.em (gld${EMULATION_NAME}_finish): Likewise.
* ldlang.c (lang_map): Use %V to print region origin.
(lang_one_common): Don't use sprintf_vma.
* ldmisc.c (vfinfo): Don't use fprintf_vma or sprintf_vma.
* pe-dll.c (pe_dll_generate_def_file): Likewise.
gdb/
* remote.c (remote_target::trace_set_readonly_regions): Replace
uses of sprintf_vma with bfd_sprintf_vma.
Currently md_end is typically used for some final actions rather than
freeing memory like other *_end functions. Rename it to md_finish,
and rename target implementation. The renaming of target functions
makes it possible to find them all with "grep md_finish",
eg. md_mips_end is renamed to mips_md_finish, not md_mips_finish.
This patch leaves a number of md_end functions unchanged, those that
either do nothing or deallocate memory, and calls them late.
The idea here is that target maintainers implement md_end functions to
tidy memory, if anyone cares. Freeing persistent memory in gas is
not at all important, except that it can hide more important memory
leaks, those that happen once per some frequent gas operation, amongst
these unimportant memory leaks.
* as.c (main): Rename md_end to md_finish.
* config/tc-alpha.c, * config/tc-alpha.h,
* config/tc-arc.c, * config/tc-arc.h,
* config/tc-arm.c, * config/tc-arm.h,
* config/tc-csky.c, * config/tc-csky.h,
* config/tc-ia64.c, * config/tc-ia64.h,
* config/tc-mcore.c, * config/tc-mcore.h,
* config/tc-mips.c, * config/tc-mips.h,
* config/tc-mmix.c, * config/tc-mmix.h,
* config/tc-msp430.c, * config/tc-msp430.h,
* config/tc-nds32.c, * config/tc-nds32.h,
* config/tc-ppc.c, * config/tc-ppc.h,
* config/tc-pru.c, * config/tc-pru.h,
* config/tc-riscv.c, * config/tc-riscv.h,
* config/tc-s390.c, * config/tc-s390.h,
* config/tc-sparc.c, * config/tc-sparc.h,
* config/tc-tic4x.c, * config/tc-tic4x.h,
* config/tc-tic6x.c, * config/tc-tic6x.h,
* config/tc-v850.c, * config/tc-v850.h,
* config/tc-xtensa.c, * config/tc-xtensa.h,
* config/tc-z80.c, * config/tc-z80.h: Similarly.
* output-file.c (output_file_close): Call md_end.
MIPS should not be using BFD_RELOC_16 for its R_MIPS_16 relocation,
since R_MIPS_16 specifies a 16-bit field in a 32-bit word.
BFD_RELOC_16, emitted by generic code to handle fixups on 16-bit data
directives, expects fixups to operate on the whole of a 16-bit word.
This patch corrects the problem by using BFD_RELOC_MIPS_16, a new bfd
reloc that is used to generate R_MIPS_16. BFD_RELOC_16 is handled in
md_apply_fix for cases where the fixup can be applied at assembly
time. Like BFD_RELOC_8, BFD_RELOC_16 now has no corresponding object
file relocation, and thus .half, .hword, .short and .dc.w must be
resolved at assembly time. BFD_RELOC_MIPS_REL16 is removed by this
patch since it isn't used.
PR 3243
PR 26542
* reloc.c (BFD_RELOC_MIPS_16): Rename from BFD_RELOC_MIPS_REL16.
* elf32-mips.c (mips_reloc_map): Map BFD_RELOC_MIPS_16 to R_MIPS_16.
* elf64-mips.c (mips_reloc_map): Likewise, delete BFD_RELOC_MIPS_REL16.
* elfn32-mips.c (mips_reloc_map): Likewise.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-mips.c (append_insn): Handle BFD_RELOC_MIPS_16.
(macro_build): Likewise.
(mips_percent_op <%half>): Generate BFD_RELOC_MIPS_16.
(md_apply_fix): Handle BFD_RELOC_16 and BFD_RELOC_MIPS_16 when fx_done.
ld/
* testsuite/ld-mips-elf/reloc-local-overflow.d,
* testsuite/ld-mips-elf/reloc-local-overflow.s: Rewrite.
With the sole user of the return value gone, convert the return type to
void. This in turn allows simplifying another construct, by moving it
slightly later in the function.
These were used originally to represent "# <line> <file>" constructs
inserted by (typically) compilers when pre-processing. Quite some time
ago they were replaced by .linefile though. Since the original
directives were never documented, we ought to be able to remove support
for them. As a result in a number of case function parameter aren't used
anymore and can hence be dropped.
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.
gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'. Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
Fix an issue caused by commit f9419b056f ("MIPS gas: code cleanup"),
<https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace
the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR.
While the register referred by its number is $31 in both cases, these
instructions operate on the floating-point control register file rather
than general-purpose registers.
gas/
* config/tc-mips.c (FCSR): New macro.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
Some versions of gcc with -Werror=format-overflow complain about using
a perfectly good 7 char buffer for "r%dr%d" when the int is between 0
and 64, apparently not seeing the value range.
note: __builtin___sprintf_chk output between 5 and 24 bytes into a destination of size 7
* config/tc-arc.c (declare_register_set): Avoid false positive
format-overflow warning.
* config/tc-epiphany.c (md_assemble): Likewise.
* config/tc-mips.c (md_begin): Likewise.
* config/tc-mmix.c (mmix_md_begin): Likewise.
* config/tc-nds32.c (nds32_elf_append_relax_relocs): Avoid false
positive "may be used uninitialized" warning.
Ever since commit 4d7206a284 ("Rework MIPS macro relaxation, fix string
merging bug"), <https://sourceware.org/ml/binutils/2004-01/msg00248.html>,
`prev_reloc_op_frag' has only been set and never used. Remove it then.
gas/
* config/tc-mips.c (prev_reloc_op_frag): Remove variable.
(my_getSmallExpression): Adjust accordingly.
This patch arranges for symbols defined in .sdata and .sbss to be
reported by nm with 'g' and 's' flags, for coff targets that support
.sdata and .sbss.
The assembler changes regarding SEC_SMALL_DATA are really just
documentation. As far as I'm aware, this won't change any assembler
output.
bfd/
* coff-alpha.c (alpha_ecoff_le_vec): Add SEC_SMALL_DATA to
applicable section flags.
* coff-mips.c (mips_ecoff_le_vec, mips_ecoff_be_vec): Likewise.
(mips_ecoff_bele_vec): Likewise.
* coffcode.h (sec_to_styp_flags): Set SEC_SMALL_DATA for .sdata
and .sbss sections.
* ecoff.c (_bfd_ecoff_new_section_hook): Likewise.
(_bfd_ecoff_styp_to_sec_flags): Likewise.
gas/
* config/tc-m32r.c (md_begin): Set SEC_SMALL_DATA on .scommon section.
* config/tc-mips.c (s_change_sec): Set SEC_SMALL_DATA for .sdata
and .sbss sections.
* config/tc-score.c: Delete !BFD_ASSEMBLER code throughout.
(s3_s_change_sec): Set SEC_SMALL_DATA for .sbss section.
(s3_s_score_lcomm): Likewise.
* config/tc-score7.c: Similarly.
* read.c (bss_alloc): Set SEC_SMALL_DATA for .sbss section.
When there is multi-labels on the same insn, the current code
will take care about the last one. it may cause that no sync
is added at the target.
Here we scan all labels with same value of
S_GET_VALUE(label_list->label)
by label_list->next.
2020-02-28 YunQiang Su <syq@debian.org>
PR gas/25539
* config/tc-mips.c (fix_loongson3_llsc): Compare label value
to handle multi-labels.
(has_label_name): New.
Clang's integrated assembler supports multiple section with the same
name:
.section .text,"ax",@progbits,unique,1
nop
.section .text,"ax",@progbits,unique,2
nop
"unique,N" assigns the number, N, as the section ID, to a section. The
valid values of the section ID are between 0 and 4294967295. It can be
used to distinguish different sections with the same section name.
This is useful with -fno-unique-section-names -ffunction-sections.
-ffunction-sections by default generates .text.foo, .text.bar, etc.
Using the same string can save lots of space in .strtab.
This patch adds section_id to bfd_section and reuses the linker
internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler
internal use to mark valid section_id. It also updates objdump to
compare section pointers if 2 sections comes from the same file since
2 different sections can have the same section name.
bfd/
PR gas/25380
* bfd-in2.h: Regenerated.
* ecoff.c (bfd_debug_section): Add section_id.
* section.c (bfd_section): Add section_id.
(SEC_ASSEMBLER_SECTION_ID): New.
(BFD_FAKE_SECTION): Add section_id.
binutils/
PR gas/25380
* objdump.c (sym_ok): Return FALSE if 2 sections are in the
same file with different section pointers.
gas/
PR gas/25380
* config/obj-elf.c (section_match): Removed.
(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
section_id.
(obj_elf_change_section): Replace info and group_name arguments
with match_p. Also update the section ID and flags from match_p.
(obj_elf_section): Handle "unique,N". Update call to
obj_elf_change_section.
* config/obj-elf.h (elf_section_match): New.
(obj_elf_change_section): Updated.
* config/tc-arm.c (start_unwind_section): Update call to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texi: Document "unique,N" in .section directive.
* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
* testsuite/gas/elf/section15.d: New file.
* testsuite/gas/elf/section15.s: Likewise.
* testsuite/gas/elf/section16.s: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
* testsuite/gas/elf/section17.d: Likewise.
* testsuite/gas/elf/section17.l: Likewise.
* testsuite/gas/elf/section17.s: Likewise.
* testsuite/gas/i386/unique.d: Likewise.
* testsuite/gas/i386/unique.s: Likewise.
* testsuite/gas/i386/x86-64-unique.d: Likewise.
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.
ld/
PR gas/25380
* testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section
directives.
* testsuite/ld-i386/tls-gd1.S: Likewise.
* testsuite/ld-x86-64/pr21481b.S: Likewise.
gas/
* config/tc-mips.c (mips_move_labels): Retain ISA mode bit
when moving labels in text segments.
(mips_align): Indicate text mode when aligning labels in
text segments.
* gas/testsuite/gas/mips/insn-isa-mode.d: New test.
* gas/testsuite/gas/mips/insn-isa-mode.s: New test source.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
git commit f2d4ba38f5 caused many failures for mips-sgi-irix targets,
and added a new test that failed for aarch64, nds32, and rl78.
The mips failures are due to BSF_OBJECT being set in many cases for
symbols by the mips .global/.globl directive. This patch removes that
code and instead sets BSF_OBJECT in a target frob_symbol function,
also moving the mips hacks in elf_frob_symbol to the new function.
Note that common symbols are handled fine in elf.c:swap_out_syms
without needing to set BSF_OBJECT, so that old code can disappear.
* config/obj-elf.c (elf_frob_symbol): Remove mips hacks.
* config/tc-mips.h (tc_frob_symbol): Define.
(mips_frob_symbol): Declare.
* config/tc-mips.c (s_mips_globl): Don't set BSF_OBJECT for irix.
(mips_frob_symbol): Fudge symbols for irix here.
* testsuite/gas/elf/type-2.e: Allow random target symbols.
