e6a8ae900b
The AArch64 implementation of 128-bit atomics is broken. For 128-bit atomics we rely on pthread barriers to correct guard the address in the pointer to get correct memory ordering. However for 128-bit atomics the address under the lock is different from the original pointer. This means that one of the values under the atomic operation is not protected properly and so we fail during when the user has requested sequential consistency as there's no barrier to enforce this requirement. As such users have resorted to adding an #ifdef GCC <emit barrier> #endif around the use of these atomics. This corrects the issue by issuing a barrier only when __ATOMIC_SEQ_CST was requested. To remedy this performance hit I think we should revisit using a similar approach to out-line-atomics for the 128-bit atomics. Note that I believe I need the empty file due to the include_next chain but I am not entirely sure. I have hand verified that the barriers are inserted for atomic seq cst. libatomic/ChangeLog: PR target/102218 * config/aarch64/aarch64-config.h: New file. * config/aarch64/host-config.h: New file. |
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