1f641d6aba
The LSE2 ifunc for 16-byte atomic load requires a barrier before the LDP - without it, it effectively has Load-AcquirePC semantics similar to LDAPR, which is less restrictive than what __ATOMIC_SEQ_CST requires. This patch fixes this and adds comments to make it easier to see which sequence is used for each case. Use a load/store exclusive loop for store to simplify testing memory ordering is correct (it is slightly faster too). libatomic/ PR libgcc/108891 * config/linux/aarch64/atomic_16.S: Fix libat_load_16_i1. Add comments describing the memory order. |
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| aarch64 | ||
| arm | ||
| ia64 | ||
| linux | ||
| mingw | ||
| nvptx | ||
| posix | ||
| powerpc | ||
| rtems | ||
| s390 | ||
| x86 | ||
| t-aix | ||