GCC modified for the FreeChainXenon project
d3c24e9e55
This patch would like to fix one ICE for __attribute__((target("arch=+v"))
and likewise extension(s). Given we have sample code as below:
void __attribute__((target("arch=+v")))
test_2 (int *a, int *b, int *out, unsigned count)
{
unsigned i;
for (i = 0; i < count; i++)
out[i] = a[i] + b[i];
}
It will have ICE when build with -march=rv64gc -O3.
test.c: In function ‘test_2’:
test.c:4:1: internal compiler error: Floating point exception
4 | {
| ^
0x1a5891b crash_signal
.../__RISC-V_BUILD__/../gcc/toplev.cc:319
0x7f0a7884251f ???
./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0x1f51ba4 riscv_hard_regno_nregs
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:8143
0x1967bb9 init_reg_modes_target()
.../__RISC-V_BUILD__/../gcc/reginfo.cc:471
0x13fc029 init_emit_regs()
.../__RISC-V_BUILD__/../gcc/emit-rtl.cc:6237
0x1a5b83d target_reinit()
.../__RISC-V_BUILD__/../gcc/toplev.cc:1936
0x35e374d save_target_globals()
.../__RISC-V_BUILD__/../gcc/target-globals.cc:92
0x35e381f save_target_globals_default_opts()
.../__RISC-V_BUILD__/../gcc/target-globals.cc:122
0x1f544cc riscv_save_restore_target_globals(tree_node*)
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:9138
0x1f55c36 riscv_set_current_function
...
There are two reasons for this ICE.
1. The implied extension(s) of v are not well handled and the
TARGET_MIN_VLEN is 0 which is not reinitialized. Then the
size / TARGET_MIN_VLEN will have DivideByZero.
2. The machine modes of the vector types will be vary after
the v extension is introduced.
This patch passed below testsuite:
1. The riscv fully regression test.
PR target/114352
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
Replace implied, combine and check to func finalize.
(riscv_subset_list::finalize): New func impl to take care of
implied, combine ext and related checks.
* config/riscv/riscv-subset.h: Add func decl for finalize.
* config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
Finalize the ext before return succeed.
* config/riscv/riscv.cc (riscv_set_current_function): Reinit the
machine mode before when set cur function.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr114352-1.c: New test.
* gcc.target/riscv/rvv/base/pr114352-2.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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