GCC modified for the FreeChainXenon project
ab0386679f
It is possible that the Zba optimization pattern zero_extendsidi2_bitmanip matches for a XTheadMemIdx INSN with the effect of emitting an invalid instruction as reported in PR116035. The pattern above is used to emit a zext.w instruction to zero-extend SI mode registers to DI mode. A similar functionality can be achieved by XTheadBb's th.extu instruction. And indeed, we have the equivalent pattern in thead.md (zero_extendsidi2_th_extu). However, that pattern depends on !TARGET_XTHEADMEMIDX. To compensate for that, there are specific patterns that ensure that zero-extension instruction can still be emitted (th_memidx_bb_zero_extendsidi2 and friends). While we could implement something similar (th_memidx_zba_zero_extendsidi2) it would only make sense, if there existed real HW that does implement Zba and XTheadMemIdx, but not XTheadBb. Unless such a machine exists, let's simply disable zero_extendsidi2_bitmanip if XTheadMemIdx is available. PR target/116035 gcc/ChangeLog: * config/riscv/bitmanip.md: Disable zero_extendsidi2_bitmanip for XTheadMemIdx. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr116035-1.c: New test. * gcc.target/riscv/pr116035-2.c: New test. (cherry picked from commit 9817d29cd66762893782a52b2c304c5083bc0023) Reported-by: Patrick O'Neill <patrick@rivosinc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> |
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