aa7543832a
libjava: * configure.in: Define SLOW_PTHREAD_SELF if configure.host set slow_pthread_self. Set up symlink for sysdeps directory. * configure.host: Document more shell variables. Set sysdeps_dir for most platforms. Set slow_pthread_self for i686. Set enable_hash_synchronization_default and slow_pthread_self for PowerPC. * posix-threads.cc (_Jv_ThreadSelf_out_of_line): Use release_set so that memory barrier is emitted where required. * include/posix-threads.h (_Jv_ThreadSelf for SLOW_PTHREAD_SELF): Add read_barrier() to enforce ordering of reads. * sysdep/powerpc/locks.h: New file. Implementation of synchronization primitives for PowerPC. * sysdep/i386/locks.h: New file. Synchronization primitives for i386 moved from natObject.cc. * sysdep/alpha/locks.h: Likewise. * sysdep/ia64/locks.h: Likewise. * sysdep/generic/locks.h: Likewise. * java/lang/natObject.cc: Move thread synchronization primitives to system-dependent headers. gcc/java: * decl.c (java_init_decl_processing): Make sure class_type_node alignment is not less than 64 bits if hash synchronization is enabled. boehm-gc: * include/gc_priv.h: Define ALIGN_DOUBLE on 32 bit targets if GCJ support is enabled, for hash synchronization. [[Split portion of a mixed commit.]] From-SVN: r50518.2
65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
// locks.h - Thread synchronization primitives. X86 implementation.
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/* Copyright (C) 2002 Free Software Foundation
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This file is part of libgcj.
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This software is copyrighted work licensed under the terms of the
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Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
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details. */
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#ifndef __SYSDEP_LOCKS_H__
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#define __SYSDEP_LOCKS_H__
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typedef size_t obj_addr_t; /* Integer type big enough for object */
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/* address. */
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// Atomically replace *addr by new_val if it was initially equal to old.
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// Return true if the comparison succeeded.
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// Assumed to have acquire semantics, i.e. later memory operations
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// cannot execute before the compare_and_swap finishes.
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inline static bool
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compare_and_swap(volatile obj_addr_t *addr,
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obj_addr_t old,
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obj_addr_t new_val)
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{
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char result;
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__asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
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: "+m"(*(addr)), "=q"(result)
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: "r" (new_val), "a"(old)
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: "memory");
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return (bool) result;
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}
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// Set *addr to new_val with release semantics, i.e. making sure
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// that prior loads and stores complete before this
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// assignment.
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// On X86, the hardware shouldn't reorder reads and writes,
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// so we just have to convince gcc not to do it either.
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inline static void
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release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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{
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__asm__ __volatile__(" " : : : "memory");
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*(addr) = new_val;
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}
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// Compare_and_swap with release semantics instead of acquire semantics.
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// On many architecture, the operation makes both guarantees, so the
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// implementation can be the same.
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inline static bool
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compare_and_swap_release(volatile obj_addr_t *addr,
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obj_addr_t old,
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obj_addr_t new_val)
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{
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return compare_and_swap(addr, old, new_val);
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}
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// Ensure that subsequent instructions do not execute on stale
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// data that was loaded from memory before the barrier.
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// On X86, the hardware ensures that reads are properly ordered.
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inline static void
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read_barrier()
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{
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}
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#endif
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