GCC modified for the FreeChainXenon project
9349aefa1d
The following testcase ICEs with LSE atomics. The problem is that the @atomic_compare_and_swap<mode> expander uses aarch64_reg_or_zero predicate for the desired operand, which is fine, given that for most of the modes and even for TImode in some cases it can handle zero immediate just fine, but the TImode @aarch64_compare_and_swap<mode>_lse just uses register_operand for that operand instead, again intentionally so, because the casp, caspa, caspl and caspal instructions need to use a pair of consecutive registers for the operand and xzr is just one register and we can't just store zero into the link register to emulate pair of zeros. So, the following patch fixes that by forcing the newval operand into a register for the TImode LSE case. 2024-03-14 Jakub Jelinek <jakub@redhat.com> PR target/114310 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For TImode force newval into a register. * gcc.dg/pr114310.c: New test. |
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