gcc/gcc/testsuite/gcc.target/sparc/vec-init-2-vis2.c at 79cad86dca731ab4d8d0ea57e3436a4c7eca224d - FreeChainXenon/gcc - Aiden Isik's Forgejo Server

FreeChainXenon/gcc

David S. Miller 79cad86dca More improvements to sparc VIS vec_init code generation.

gcc/

	* config/sparc/sparc.md (UNSPEC_SHORT_LOAD): New unspec.
	(zero-extend_v8qi_vis, zero_extend_v4hi_vis): New expanders.
	(*zero_extend_v8qi_<P:mode>_insn,
	*zero_extend_v4hi_<P:mode>_insn): New insns.
	* config/sparc/sparc.c (vector_init_move_words,
	vector_init_prepare_elts, sparc_expand_vector_init_vis2,
	sparc_expand_vector_init_vis1): New functions.
	(vector_init_bshuffle): Rewrite to handle more cases and make use
	of locs[] array prepared by vector_init_prepare_elts.
	(vector_init_fpmerge, vector_init_faligndata): Delete.
	(sparc_expand_vector_init): Rewrite using new infrastructure.

gcc/testsuite/

	* lib/test-supports.exp
	(check_effective_target_ultrasparc_vis2_hw): New proc.
	(check_effective_target_ultrasparc_vis3_hw): New proc.
	* gcc.target/sparc/vec-init-1.inc: New vector init common code.
	* gcc.target/sparc/vec-init-2.inc: Likewise.
	* gcc.target/sparc/vec-init-3.inc: Likewise.
	* gcc.target/sparc/vec-init-1-vis1.c: New test.
	* gcc.target/sparc/vec-init-1-vis2.c: New test.
	* gcc.target/sparc/vec-init-1-vis3.c: New test.
	* gcc.target/sparc/vec-init-2-vis1.c: New test.
	* gcc.target/sparc/vec-init-2-vis2.c: New test.
	* gcc.target/sparc/vec-init-2-vis3.c: New test.
	* gcc.target/sparc/vec-init-3-vis1.c: New test.
	* gcc.target/sparc/vec-init-3-vis2.c: New test.
	* gcc.target/sparc/vec-init-3-vis3.c: New test.

From-SVN: r181024

2011-11-05 19:39:03 -07:00

5 lines

149 B

C

Raw Blame History

 /* { dg-do run } */
 /* { dg-require-effective-target ultrasparc_vis2_hw } */
 /* { dg-options "-mcpu=ultrasparc3 -O2" } */
 #include "vec-init-2.inc"