GCC modified for the FreeChainXenon project
4ff5e7cec9
> > This patch is still work in progress, but posting to show failure with > > bitint-7 test where handle_stmt called from lower_mergeable_stmt ICE's > > because the idx (3) is out of range for the __BitInt(135) with a limb_prec > > of 64. > > I can reproduce it, will debug it momentarily. So, the problem was that in 2 spots I was comparing TYPE_SIZE of large/huge BITINT_TYPEs to determine if it can be handled cheaply. On x86_64 with limb_mode == abi_limb_mode (both DImode) that works fine, if TYPE_SIZE is equal, it means it has the same number of limbs. But on aarch64 TYPE_SIZE of say _BitInt(135) and _BitInt(193) is the same, both are 256-bit storage, but because DImode is used as limb_mode, the former actually needs just 3 limbs, while the latter needs 4 limbs. And limb_access_type was asserting that we don't try to access 4th limb on types which actually have a precision which needs just 3 limbs. The following patch should fix that. Note, for the info.extended targets (currently none, but I think arm 32-bit in the ABI is meant like that), we'll need to do something different, because the upper bits aren't just padding and should be zero/sign extended, so if we say have limb_mode SImode, abi_limb_mode DImode, we'll need to treat _BitInt(135) not as 5 SImode limbs, but 6. For !info.extended targets I think treating _BitInt(135) as 3 DImode limbs rather than 4 is fine. 2024-01-12 Jakub Jelinek <jakub@redhat.com> * gimple-lower-bitint.cc (mergeable_op): Instead of comparing TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare CEIL (TYPE_PRECISION (t), limb_prec). (bitint_large_huge::handle_cast): Likewise. |
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