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175650 commits

Author SHA1 Message Date
Claudiu Zissulescu
d08a318b4f arc: Cleanup compilation warning
gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
2020-03-31 15:00:32 +03:00
Srinath Parvathaneni
1ef979c696 [ARM][PATCH]: Add MVE ACLE intrinsics vbicq_n_* polymorphic variant support.
For the following MVE ACLE intrinsics, polymorphic variant support is missing on the trunk.

vbicq_n_s16, vbicq_n_s32, vbicq_n_u16 and vbicq_n_u32.

This patch add the polymorphic variant support for above intrinsics.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
	variant.
	(__arm_vbicq): Likewise.

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Modify.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
2020-03-31 11:08:22 +01:00
Claudiu Zissulescu
cea1fc6f67 arc: Allow more ABIs in GLIBC_DYNAMIC_LINKER
Enable big-endian suffixed dynamic linker per glibc multi-abi support.

And to avoid a future churn and version pairingi hassles, also allow
arc700 although glibc for ARC currently doesn't support it.

gcc/
xxxx-xx-xx  Vineet Gupta <vgupta@synopsys.com>

       * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
2020-03-31 13:04:49 +03:00
Srinath Parvathaneni
e81d0d9ec7 [ARM][PATCH]: Add support for MVE ACLE intrinsics polymorphic variants for +mve.fp option.
For the following MVE ACLE intrinsics, polymorphic variant supports only +mve option, support for +mve.fp is missing.

vabavq_p_s16, vabavq_p_s32, vabavq_p_s8, vabavq_p_u16, vabavq_p_u32, vabavq_p_u8, vabavq_s16, vabavq_s32, vabavq_s8, vabavq_u16, vabavq_u32, vabavq_u8, vaddlvaq_p_s32, vaddlvaq_p_u32, vaddlvaq_s32, vaddlvaq_u32, vaddlvq_p_s32, vaddlvq_p_u32, vaddlvq_u32, vaddvaq_p_s16, vaddvaq_p_s32, vaddvaq_p_s8, vaddvaq_p_u16, vaddvaq_p_u32, vaddvaq_p_u8, vaddvaq_s16, vaddvaq_s32, vaddvaq_s8, vaddvaq_u16, vaddvaq_u32, vaddvaq_u8, vaddvq_p_s16, vaddvq_p_s32, vaddvq_p_s8, vaddvq_p_u16, vaddvq_p_u32, vaddvq_p_u8, vaddvq_s8, vaddvq_u16, vaddvq_u32, vaddvq_u8, vcmpcsq_m_n_u16, vcmpcsq_m_n_u32, vcmpcsq_m_n_u8, vcmpcsq_m_u16, vcmpcsq_m_u32, vcmpcsq_m_u8, vcmpcsq_n_u16, vcmpcsq_n_u32, vcmpcsq_n_u8, vcmpcsq_u16, vcmpcsq_u32, vcmpcsq_u8, vcmpeqq_n_f16, vcmpeqq_n_f32, vcmpgeq_m_n_s16, vcmpgeq_m_n_s32, vcmpgeq_m_n_s8, vcmpgtq_m_n_f16, vcmpgtq_m_n_f32, vcmpgtq_n_f16, vcmpgtq_n_f32, vcmphiq_m_n_u16, vcmphiq_m_n_u32, vcmphiq_m_n_u8, vcmphiq_m_u16, vcmphiq_m_u32, vcmphiq_m_u8, vcmphiq_n_u16, vcmphiq_n_u32, vcmphiq_n_u8, vcmphiq_u16, vcmphiq_u32, vcmphiq_u8, vcmpleq_m_n_f16, vcmpleq_m_n_f32, vcmpleq_n_f16, vcmpleq_n_f32, vcmpltq_m_n_f16, vcmpltq_m_n_f32, vcmpneq_m_n_f16, vcmpneq_m_n_f32, vcmpneq_n_f16, vcmpneq_n_f32, vmaxavq_p_s16, vmaxavq_p_s32, vmaxavq_p_s8, vmaxavq_s16, vmaxavq_s32, vmaxavq_s8, vmaxq_x_s16, vmaxq_x_s32, vmaxq_x_s8, vmaxq_x_u16, vmaxq_x_u32, vmaxq_x_u8, vmaxvq_p_s16, vmaxvq_p_s32, vmaxvq_p_s8, vmaxvq_p_u16, vmaxvq_p_u32, vmaxvq_p_u8, vmaxvq_s16, vmaxvq_s32, vmaxvq_s8, vmaxvq_u16, vmaxvq_u32, vmaxvq_u8, vminavq_p_s16, vminavq_p_s32, vminavq_p_s8, vminavq_s16, vminavq_s32, vminavq_s8, vminq_x_s16, vminq_x_s32, vminq_x_s8, vminq_x_u16, vminq_x_u32, vminq_x_u8, vminvq_p_s16, vminvq_p_s32, vminvq_p_s8, vminvq_p_u16, vminvq_p_u32, vminvq_p_u8, vminvq_s16, vminvq_s32, vminvq_s8, vminvq_u16, vminvq_u32, vminvq_u8, vmladavaq_p_s16, vmladavaq_p_s32, vmladavaq_p_s8, vmladavaq_p_u16, vmladavaq_p_u32, vmladavaq_p_u8, vmladavaq_s16, vmladavaq_s32, vmladavaq_s8, vmladavaq_u16, vmladavaq_u32, vmladavaq_u8, vmladavaxq_s16, vmladavaxq_s32, vmladavaxq_s8, vmladavq_p_s16, vmladavq_p_s32, vmladavq_p_s8, vmladavq_p_u16, vmladavq_p_u32, vmladavq_p_u8, vmladavq_s16, vmladavq_s32, vmladavq_s8, vmladavq_u16, vmladavq_u32, vmladavq_u8, vmladavxq_p_s16, vmladavxq_p_s32, vmladavxq_p_s8, vmladavxq_s16, vmladavxq_s32, vmladavxq_s8, vmlaldavaq_s16, vmlaldavaq_s32, vmlaldavaq_u16, vmlaldavaq_u32, vmlaldavaxq_s16, vmlaldavaxq_s32, vmlaldavq_p_s16, vmlaldavq_p_s32, vmlaldavq_p_u16, vmlaldavq_p_u32, vmlaldavq_s16, vmlaldavq_s32, vmlaldavq_u16, vmlaldavq_u32, vmlaldavxq_p_s16, vmlaldavxq_p_s32, vmlsdavaq_s16, vmlsdavaq_s32, vmlsdavaq_s8, vmlsdavaxq_s16, vmlsdavaxq_s32, vmlsdavaxq_s8, vmlsdavq_p_s16, vmlsdavq_p_s32, vmlsdavq_p_s8, vmlsdavq_s16, vmlsdavq_s32, vmlsdavq_s8, vmlsdavxq_p_s16, vmlsdavxq_p_s32, vmlsdavxq_p_s8, vmlsdavxq_s16, vmlsdavxq_s32, vmlsdavxq_s8, vmlsldavaq_s16, vmlsldavaq_s32, vmlsldavaxq_s16, vmlsldavaxq_s32, vmlsldavq_p_s16, vmlsldavq_p_s32, vmlsldavq_s16, vmlsldavq_s32, vmlsldavxq_p_s16, vmlsldavxq_p_s32, vmlsldavxq_s16, vmlsldavxq_s32, vmovlbq_x_s16, vmovlbq_x_s8, vmovlbq_x_u16, vmovlbq_x_u8, vmovltq_x_s16, vmovltq_x_s8, vmovltq_x_u16, vmovltq_x_u8, vmulhq_x_s16, vmulhq_x_s32, vmulhq_x_s8, vmulhq_x_u16, vmulhq_x_u32, vmulhq_x_u8, vmullbq_int_x_s16, vmullbq_int_x_s32, vmullbq_int_x_s8, vmullbq_int_x_u16, vmullbq_int_x_u32, vmullbq_int_x_u8, vmullbq_poly_x_p16, vmullbq_poly_x_p8, vmulltq_int_x_s16, vmulltq_int_x_s32, vmulltq_int_x_s8, vmulltq_int_x_u16, vmulltq_int_x_u32, vmulltq_int_x_u8, vmulltq_poly_x_p16, vmulltq_poly_x_p8, vrmlaldavhaq_s32, vrmlaldavhaq_u32, vrmlaldavhaxq_s32, vrmlaldavhq_p_s32, vrmlaldavhq_p_u32, vrmlaldavhq_s32, vrmlaldavhq_u32, vrmlaldavhxq_p_s32, vrmlaldavhxq_s32, vrmlsldavhaq_s32, vrmlsldavhaxq_s32, vrmlsldavhq_p_s32, vrmlsldavhq_s32, vrmlsldavhxq_p_s32, vrmlsldavhxq_s32, vstrbq_p_s16, vstrbq_p_s32, vstrbq_p_s8, vstrbq_p_u16, vstrbq_p_u32, vstrbq_p_u8, vstrbq_s16, vstrbq_s32, vstrbq_s8, vstrbq_scatter_offset_p_s16, vstrbq_scatter_offset_p_s32, vstrbq_scatter_offset_p_s8, vstrbq_scatter_offset_p_u16, vstrbq_scatter_offset_p_u32, vstrbq_scatter_offset_p_u8, vstrbq_scatter_offset_s16, vstrbq_scatter_offset_s32, vstrbq_scatter_offset_s8, vstrbq_scatter_offset_u16, vstrbq_scatter_offset_u32, vstrbq_scatter_offset_u8, vstrbq_u16, vstrbq_u32, vstrbq_u8, vstrdq_scatter_base_p_s64, vstrdq_scatter_base_p_u64, vstrdq_scatter_base_s64, vstrdq_scatter_base_u64, vstrdq_scatter_offset_p_s64, vstrdq_scatter_offset_p_u64, vstrdq_scatter_offset_s64, vstrdq_scatter_offset_u64, vstrdq_scatter_shifted_offset_p_s64,
vstrdq_scatter_shifted_offset_p_u64, vstrdq_scatter_shifted_offset_s64,
vstrdq_scatter_shifted_offset_u64.

This patch adds the support for MVE ACLE intrinsics polymorphic variants with +mve.fp option.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
	common section of both MVE Integer and MVE Floating Point.
	(vaddvq): Likewise.
	(vaddlvq_p): Likewise.
	(vaddvaq): Likewise.
	(vaddvq_p): Likewise.
	(vcmpcsq): Likewise.
	(vmlsdavxq): Likewise.
	(vmlsdavq): Likewise.
	(vmladavxq): Likewise.
	(vmladavq): Likewise.
	(vminvq): Likewise.
	(vminavq): Likewise.
	(vmaxvq): Likewise.
	(vmaxavq): Likewise.
	(vmlaldavq): Likewise.
	(vcmphiq): Likewise.
	(vaddlvaq): Likewise.
	(vrmlaldavhq): Likewise.
	(vrmlaldavhxq): Likewise.
	(vrmlsldavhq): Likewise.
	(vrmlsldavhxq): Likewise.
	(vmlsldavxq): Likewise.
	(vmlsldavq): Likewise.
	(vabavq): Likewise.
	(vrmlaldavhaq): Likewise.
	(vcmpgeq_m_n): Likewise.
	(vmlsdavxq_p): Likewise.
	(vmlsdavq_p): Likewise.
	(vmlsdavaxq): Likewise.
	(vmlsdavaq): Likewise.
	(vaddvaq_p): Likewise.
	(vcmpcsq_m_n): Likewise.
	(vcmpcsq_m): Likewise.
	(vmladavxq_p): Likewise.
	(vmladavq_p): Likewise.
	(vmladavaxq): Likewise.
	(vmladavaq): Likewise.
	(vminvq_p): Likewise.
	(vminavq_p): Likewise.
	(vmaxvq_p): Likewise.
	(vmaxavq_p): Likewise.
	(vcmphiq_m): Likewise.
	(vaddlvaq_p): Likewise.
	(vmlaldavaq): Likewise.
	(vmlaldavaxq): Likewise.
	(vmlaldavq_p): Likewise.
	(vmlaldavxq_p): Likewise.
	(vmlsldavaq): Likewise.
	(vmlsldavaxq): Likewise.
	(vmlsldavq_p): Likewise.
	(vmlsldavxq_p): Likewise.
	(vrmlaldavhaxq): Likewise.
	(vrmlaldavhq_p): Likewise.
	(vrmlaldavhxq_p): Likewise.
	(vrmlsldavhaq): Likewise.
	(vrmlsldavhaxq): Likewise.
	(vrmlsldavhq_p): Likewise.
	(vrmlsldavhxq_p): Likewise.
	(vabavq_p): Likewise.
	(vmladavaq_p): Likewise.
	(vstrbq_scatter_offset): Likewise.
	(vstrbq_p): Likewise.
	(vstrbq_scatter_offset_p): Likewise.
	(vstrdq_scatter_base_p): Likewise.
	(vstrdq_scatter_base): Likewise.
	(vstrdq_scatter_offset_p): Likewise.
	(vstrdq_scatter_offset): Likewise.
	(vstrdq_scatter_shifted_offset_p): Likewise.
	(vstrdq_scatter_shifted_offset): Likewise.
	(vmaxq_x): Likewise.
	(vminq_x): Likewise.
	(vmovlbq_x): Likewise.
	(vmovltq_x): Likewise.
	(vmulhq_x): Likewise.
	(vmullbq_int_x): Likewise.
	(vmullbq_poly_x): Likewise.
	(vmulltq_int_x): Likewise.
	(vmulltq_poly_x): Likewise.
	(vstrbq): Likewise.

gcc/testsuite/ChangeLog:

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Modify.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
2020-03-31 10:53:25 +01:00
Jakub Jelinek
a27c534794 aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368]
The following testcase ICEs in final_scan_insn_1.  The problem is in the
@aarch64_compare_and_swaphi define_insn_and_split, since 9 it uses
aarch64_plushi_operand predicate for the "expected value" operand, which
allows either 0..0xfff constants or 0x1000..0xf000 constants (i.e. HImode
values which when zero extended are either 0..0xfff or (0..0xfff) << 12).
The problem is that RA doesn't care about predicates, it honors just
constraints and the used constraint on the operand is n, which means any
HImode CONST_SCALAR_INT.  In the testcase LRA thus propagates the -1
value into the insn.
This is a define_insn_and_split which requires mandatory split.
But during split2 pass, we check the predicate (and don't check
constraints), which fails and thus we don't split it and during final ICE
because the mandatory splitting didn't happen.

The following patch fixes it by adding a matching constraint to the
predicate and using it.

2020-03-31  Jakub Jelinek  <jakub@redhat.com>

	PR target/94368
	* config/aarch64/constraints.md (Uph): New constraint.
	* config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
	(@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
	constraint.

	* gcc.dg/pr94368.c: New test.
2020-03-31 11:08:22 +02:00
Jakub Jelinek
1dcffc8ddc fold-const: Fix division folding with vector operands [PR94412]
The following testcase is miscompiled since 4.9, we treat unsigned
vector types as if they were signed and "optimize" negations across it.

2020-03-31  Marc Glisse  <marc.glisse@inria.fr>
	    Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/94412
	* fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
	ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.

	* gcc.c-torture/execute/pr94412.c: New test.

Co-authored-by: Marc Glisse <marc.glisse@inria.fr>
2020-03-31 11:06:43 +02:00
Jakub Jelinek
5ea39b2412 store-merging: Allow enums during bswap recognition [PR94403]
The following testcase is optimized with char/unsigned char/signed char,
but not with std::byte.  The following patch fixes that.  Didn't use
INTEGRAL_TYPE_P because bswapping bools is just too weird.

2020-03-31  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/94403
	* gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
	ENUMERAL_TYPE lhs_type.

	* g++.dg/tree-ssa/pr94403.C: New test.
2020-03-31 11:04:32 +02:00
Jakub Jelinek
56f0b32476 forwprop: Pattern recognize more rotates [PR94344]
The following patch adjusts simplify_rotate to recognize more rotates,
basically we allow even some same precision integral -> integral
conversions, with the requirement that the RSHIFT_EXPR operand has to be
done in unsigned type (i.e. logical right shift), so that we compensate for
the combiner no longer being able to simplify those into rotates on some
targets.

2020-03-31  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/94344
	* tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
	conversions, either on both operands of |^+ or just one.  Handle
	also extra same precision conversion on RSHIFT_EXPR first operand
	provided RSHIFT_EXPR is performed in unsigned type.

	* gcc.dg/pr94344.c: New test.
2020-03-31 11:02:47 +02:00
David Malcolm
3809bcd6c0 lra: set insn_code_data to NULL when freeing
libgccjit's test-threads.c repeatedly compiles and runs numerous tests,
each in a separate thread.

Attempting to add an empty test that generates no code leads to a
double-free ICE within that thread, within lra.c's
finish_insn_code_data_once.

The root cause is that the insn_code_data array is cleared in
init_insn_code_data_once, but this is only called the first time
a cgraph_node is expanded [1], whereas the "loop-over-all-elements
and free them" is unconditionally called in finalize [2].  Hence
if there are no functions:
* the array is not re-initialized for the empty context
* when finish_insn_code_data_once is called for the empty context
it still contains the freed pointers from the previous context
that held the jit mutex, and hence the free is a double-free.

This patch sets the pointers to NULL after freeing them, fixing
the ICE.

[1]
init_insn_code_data_once is called via
  lra_init_once called by
    ira_init_once called by
      initialize_rtl, via:
         if (!rtl_initialized)
           ira_init_once ();
        called by init_function_start
           called by cgraph_node::expand

[2]:
finish_insn_code_data_once is called by:
  lra_finish_once called by
    finalize

gcc/ChangeLog:
	* lra.c (finish_insn_code_data_once): Set the array elements
	to NULL after freeing them.

gcc/testsuite/ChangeLog:
	* jit.dg/all-non-failing-tests.h: Add test-empty.c
2020-03-30 21:03:00 -04:00
GCC Administrator
13a29fc573 Daily bump. 2020-03-31 00:16:22 +00:00
Joseph Myers
9f6abd1b03 Update gcc sv.po.
* sv.po: Update.
2020-03-30 23:53:21 +00:00
Jason Merrill
5830f75355 c++: Fix comparison of fn() and ns::fn() [PR90711]
The resolution of CWG issue 1321 clarified that when deciding whether two
expressions involving template parameters are equivalent, two dependent
function calls where the function is named with an unqualified-id are
considered to be equivalent if the name is the same, even if unqualified
lookup finds different sets of functions.  We were wrongly treating
qualified-ids the same way, so that EXISTS and test::EXISTS were considered
to be equivalent even though they are looking up the name in different
scopes.  This also causes a mangling bug, but I don't think it's safe to fix
that for GCC 10; this patch just fixes the comparison.

gcc/cp/ChangeLog
2020-03-30  Jason Merrill  <jason@redhat.com>

	PR c++/90711
	* tree.c (cp_tree_equal) [CALL_EXPR]: Compare KOENIG_LOOKUP_P.
	(called_fns_equal): Check DECL_CONTEXT.
2020-03-30 17:04:09 -04:00
Jakub Jelinek
1cb1986cb5 c++: Fix handling of internal fn calls in statement expressions [PR94385]
The following testcase ICEs, because the FE when processing the statement
expression changes the .VEC_CONVERT internal fn CALL_EXPR into .PHI call.
That is because the internal fn call is recorded in the base.u.ifn
field, which overlaps base.u.bits.lang_flag_1 which is used for
STMT_IS_FULL_EXPR_P, so this essentially does ifn |= 2 on little-endian.
STMT_IS_FULL_EXPR_P bit is used in:
cp-gimplify.c-  if (STATEMENT_CODE_P (code))
cp-gimplify.c-    {
cp-gimplify.c-      saved_stmts_are_full_exprs_p = stmts_are_full_exprs_p ();
cp-gimplify.c-      current_stmt_tree ()->stmts_are_full_exprs_p
cp-gimplify.c:        = STMT_IS_FULL_EXPR_P (*expr_p);
cp-gimplify.c-    }
and
pt.c-  if (STATEMENT_CODE_P (TREE_CODE (t)))
pt.c:    current_stmt_tree ()->stmts_are_full_exprs_p = STMT_IS_FULL_EXPR_P (t);
so besides being wrong on some other codes, it actually isn't beneficial at
all to set it on anything else, so the following patch restricts it to
trees with STATEMENT_CODE_P TREE_CODE.

2020-03-30  Jakub Jelinek  <jakub@redhat.com>

	PR c++/94385
	* semantics.c (add_stmt): Only set STMT_IS_FULL_EXPR_P on trees with
	STATEMENT_CODE_P code.

	* c-c++-common/pr94385.c: New test.
2020-03-30 22:55:36 +02:00
Andreas Schwab
48e331d638 Define TRY_EMPTY_VM_SPACE for riscv64-linux
* config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
Define.
2020-03-30 20:54:44 +02:00
Will Schmidt
841e721579 RS6000 Allow builtin initialization regardless of mask
Disable the code that limits initialization of builtins based
on the rs6000_builtin_mask.  This allows all built-ins to be
properly referenced when building code using #pragma for cpu
targets newer than what was specified by the -mcpu default.
The use of built-ins is still properly limited by logic within
altivec_resolve_overloaded_builtin().

2020-03-30  Will Schmidt  <will_schmidt@vnet.ibm.com>

gcc/
    * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
    to skip defining builtins based on builtin_mask.

gcc/testsuite/
    * gcc.target/powerpc/pragma_power6.c: New.
    * gcc.target/powerpc/pragma_power7.c: New.
    * gcc.target/powerpc/pragma_power8.c: New.
    * gcc.target/powerpc/pragma_power9.c: New.
    * gcc.target/powerpc/pragma_misc9.c: New.
    * gcc.target/powerpc/vsu/vec-all-nez-7.c: Update error message.
    * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Update error message.
2020-03-30 12:13:57 -05:00
Will Schmidt
48c18af43f Update bswap64-4 test for desired results
Update existing testcase powerpc/bswap64-4.c to
reflect that we generate ldbrx and stdbrx instructions
for newer cpu targets, versus the pair of lwbrx and stwbrx
instructions as seen on previous cpu targets.

2020-03-24  Will Schmidt  <will_schmidt@vnet.ibm.com>

gcc/testsuite/
	* gcc.target/powerpc/bswap64-4.c: Update scan-assembler
	expected results.
2020-03-30 11:13:33 -05:00
Jakub Jelinek
5abbfd3cd3 i386: Fix up *one_cmplv*2* insn with avx512f [PR94343]
This define_insn has two issues.
One is that with -mavx512f -mno-avx512vl it can emit an AVX512VL-only insn
- 128-bit or 256-bit EVEX encoded vpternlog{d,q}.
Another one is that because there is no vpternlog{b,w}, we emit vpternlogd
instead, but then we shouldn't pretend we support masking of that, because
we don't.
The first one can be fixed by forcing the use of %zmm* registers instead of
%xmm* or %ymm* if AVX512F but not AVX512VL, like we do for a couple of other
insns (although that is primarily done in order to support %xmm16+ regs).
But we need to make sure that in that case the input operand isn't memory,
because while we can read and store the higher bits of registers, we don't
want to read from memory more bytes than what we should read.

A variant to these two if_then_else set attrs, condition in the output and
larger condition would be 4 different define_insns (one with something like
VI48_AVX512VL iterator, masking, no g modifiers and "vm" input constraint,
another one with VI48_AVX iterator, !TARGET_AVX512VL in condition,
no masking, g modifiers and "v" input constraint, one with VI12_AVX512VL
iterator, no masking, no g modifiers and "vm" input constraint and last one with
VI12_AVX2 iterator, !TARGET_AVX512VL in condition, no masking, g modifiers
and "v" input constraint, but I think having one pattern is shorter than
that.

2020-03-30  Jakub Jelinek  <jakub@redhat.com>

	PR target/94343
	* config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
	!TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
	operand is a register.  Don't enable masked variants for V*[QH]Imode.

	* gcc.target/i386/avx512f-pr94343.c: New test.
	* gcc.target/i386/avx512vl-pr94343.c: New test.
2020-03-30 18:05:01 +02:00
Martin Liska
291aa50a63
XFAIL pr57193.c test-case.
PR rtl-optimization/87716
	* gcc.target/i386/pr57193.c: XFAIL a test-case.
2020-03-30 17:49:27 +02:00
Martin Liska
3a9db91bee
Fix scan pattern of vect-8.f90 dump.
PR testsuite/94402
	* gfortran.dg/vect/vect-8.f90: Allow 22 or 23 loops
	to be vectorized (based on libmvec presence).
2020-03-30 17:49:10 +02:00
Jakub Jelinek
ec919cfcef Fix vextract* masked patterns [PR93069]
The AVX512F documentation clearly states that in instructions where the
destination is a memory only merging-masking is possible, not zero-masking,
and the assembler enforces that.

The testcase in this patch fails to assemble because of
Error: unsupported masking for `vextracti32x8'
on
        vextracti32x8   $0x0, %zmm1, -64(%rsp){%k1}{z}
For the vector extraction patterns, we apparently have 7 *_maskm patterns
that only accept memory destinations and rtx_equal_p merge-masking source
for it, 7 *<mask_name> corresponding patterns that allow memory destination
only for the non-masked cases (through <store_mask_constraint>), then 2
*<mask_name> patterns (lo ssehalf V16FI and lo ssehalf VI8F_256 ones) which
do allow memory destination even for masked cases and are the cause of the
testsuite failure, because we must not allow C constraint if the destination
is m, and finally one pair of patterns (separate * and *_mask, hi ssehalf
VI4F_256), which has another issue (for which I don't have a testcase
though), where if it would match zero-masking with register destination,
it wouldn't emit the needed {z} into assembly.
The attached patch fixes those 3 issues only, perhaps more suitable for
backporting.

2020-03-30  Jakub Jelinek  <jakub@redhat.com>

	PR target/93069
	* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
	<store_mask_constraint> instead of m in output operand constraint.
	(vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
	%{%3%}.

	* gcc.target/i386/avx512vl-pr93069.c: New test.
	* gcc.dg/vect/pr93069.c: New test.
2020-03-30 17:38:21 +02:00
Alan Modra
07c48b61a0 [RS6000] Put call cookie back in AIX/ELFv2 call patterns
-mlongcall -mno-pltseq is supposed to emit long calls by using
indirect calls.  It differs from -mlongcall -mpltseq in that the
function addresses are not placed in the PLT and thus lazy PLT
resolution is not available, affecting programs that dlopen shared
libraries.

In the case of -mcpu=future -mpcrel -mlongcall -mno-pltseq we see an
indirect call being generated, but combine merrily optimises the
sequence back to a direct call.  call_indirect_pcrel is enough like
call_nonlocal_aix that this can happen.

This patch puts the call cookie back in the call rtl, removed by git
commit f90f960ca8, in order to disable the optimisation for long
calls.  When that is done for call_local_aix the pattern becomes the
same as call_local32/64, so I merged them.  The only difference
besides mode between call_local32 and call_local64, dating back to
1998 commit a260abc996, is that call_local64 has TARGET_64BIT in the
predicate.  That alone doesn't seem reason enough to need separate
patterns; The P mode iterator selects DI on TARGET_64BIT anyway.

	* config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
	(rs6000_indirect_call_template_1): Adjust to suit.
	* config/rs6000/rs6000.md (call_local): Merge call_local32,
	call_local64, and call_local_aix.
	(call_value_local): Simlarly.
	(call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
	and disable pattern when CALL_LONG.
	(call_indirect_aix, call_value_indirect_aix): Adjust rtl.
	(call_indirect_elfv2, call_indirect_pcrel): Likewise.
	(call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
2020-03-30 18:09:05 +10:30
GCC Administrator
2a93fb6e96 Daily bump. 2020-03-30 00:16:20 +00:00
H.J. Lu
dacc7effee doc: Update -falign-functions/-falign-loops/-falign-jumps
Change -falign-functions=N to

    Align the start of functions to the next power-of-two greater than
    or equal to N.

Add

    If '-falign-labels' is greater than this value, then its value is
    used instead.

to -falign-loops=N and -falign-jumps=N.

	PR driver/94381
	* doc/invoke.texi: Update -falign-functions, -falign-loops and
	-falign-jumps documentation.
2020-03-29 15:54:53 -07:00
Iain Buclaw
60c254b279 testsuite: Handle more kinds of gdc.test test flags and directives.
This patch adds cases for JSON and D header file generation flags in the
testsuite, and sets up the test accordingly to only compile, then check
that the expected output file exists.

Support has also been added for the DFLAGS test directive, which
disables testing with all default flag permutations.

gcc/testsuite/ChangeLog:

	* lib/gdc-utils.exp: (gdc-convert-args): Handle compilation test
	arguments -D, -H, -X, and set compilable_output_file_ext.
	(gdc-convert-test): Document and add cases DFLAGS and
	EXTRA_CPP_SOURCES.  Add dg-final entry for output generation tests,
	and set compilable_do_what to compile.
	(gdc-do-test): Define compilable_do_what, default to assemble.
2020-03-29 21:43:50 +02:00
Iain Buclaw
afd9da8b8a testsuite: Move C++ tests in gdc.test into own subdirectory.
Tests have been moved into runnable_cxx as part of upstream dmd 3e10e2dd2.

The extra flags required for tests that mix C++ and D are now limited to
only a small subset of tests, rather than applied to all tests across
gdc.dg and gdc.test.

Reviewed-on: https://github.com/dlang/dmd/pull/10980

gcc/testsuite/ChangeLog:

	* gdc.test/runnable_cxx/runnable_cxx.exp: New file.
	* lib/gdc-utils.exp (gdc-do-test): Add case for runnable_cxx.
	* lib/gdc.exp (gdc_include_flags): Only add flags for libstdc++-v3 if
	GDC_INCLUDE_CXX_FLAGS is true.
	(gdc_link_flags): Likewise.
	(gdc_init): Move setting of default gdc test flags to...
	(gdc_target_compile): ...here.
2020-03-29 19:25:27 +02:00
Martin Liska
85f6f317ec
Fix typo in a warning related to flatten.
PR ipa/94363
	* cgraphunit.c (process_function_and_variable_attributes): Remove
	double 'attribute' words.
2020-03-29 19:24:33 +02:00
John David Anglin
46b7d819f7 Delete duplicate .align output.
2020-03-29  John David Anglin  <dave.anglin@bell.net>

	* gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
	.align output.
2020-03-29 16:34:59 +00:00
Iain Buclaw
c76df72f1a testsuite: Split up gdc-test.exp into each subdirectory
Use multiple test scripts, one for each subdirectory containing test
files, instead of having one test script to manage them all.

This allows removing some workarounds, such as the need to create
symlinks in the test run directory.

gcc/testsuite/ChangeLog:

	* gdc.test/compilable/compilable.exp: New file.
	* gdc.test/fail_compilation/fail_compilation.exp: New file.
	* gdc.test/gdc-test.exp: Remove.
	* gdc.test/runnable/runnable.exp: New file.
	* lib/gdc-utils.exp: ...this.  Remove load_lib gdc-dg.exp.
	(dmd2dg): Rename to...
	(gdc-convert-test): ...this.
	(gdc-do-test): Add testcases parameter and remove subdir handling.
2020-03-29 17:29:04 +02:00
GCC Administrator
673bb288e6 Daily bump. 2020-03-29 00:16:17 +00:00
Jonathan Wakely
f6b2b79040 libstdc++: Fix two tests that fail in C++20 mode
* testsuite/20_util/is_constructible/value-2.cc: Fix test to account
	for changes due to parenthesized aggregate-initialization in C++20.
	* testsuite/20_util/time_point/cons/81468.cc: Fix test to not clash
	with std::chrono::sys_time in C++20.
2020-03-28 21:52:13 +00:00
Jonathan Wakely
42cda3ba45 libstdc++: Fix std::reverse_iterator relational operators
My recent changes to reverse_iterator's comparisons was not the version
of the code (or tests) that I meant to commit, and broke the relational
operators. This fixes them to reverse the order of the comparisons on
the base() iterators.

This also replaces the SFINAE constraints in the return type of the
reverse_iterator and move_iterator comparisons with a requires-clause.
This ensures the constrained overloads are preferred to unconstrained
ones. This means the non-standard same-type overloads can be omitted for
C++20 because they're not needed to solve the problem with std::rel_ops
or the testsuite's greedy_ops::X type.

	* include/bits/stl_iterator.h (reverse_iterator): Use requires-clause
	to constrain C++20 versions of comparison operators. Fix backwards
	logic of relational operators.
	(move_iterator): Use requires-clause to constrain comparison operators
	in C++20. Do not declare non-standard same-type overloads for C++20.
	* testsuite/24_iterators/move_iterator/rel_ops_c++20.cc: Check result
	of comparisons and check using greedy_ops type.
	* testsuite/24_iterators/reverse_iterator/rel_ops_c++20.cc: Likewise.
	* testsuite/24_iterators/move_iterator/greedy_ops.cc: Remove redundant
	main function from compile-only test.
	* testsuite/24_iterators/reverse_iterator/greedy_ops.cc: Likewise.
2020-03-28 21:52:13 +00:00
Roman Zhuykov
946a444df3 testsuite: adjust modulo-sched compare-debug tests
Without this patch tortured tests eventually fail because of another
known issue which I plan to fix later in stage1.

	* gcc.dg/torture/pr87197-debug-sms.c: Move to ...
	* gcc.dg/sms-compare-debug-1.c: ... this.  Add -O2.
	* gcc.c-torture/execute/pr70127-debug-sms.c: Move to ...
	* gcc.dg/sms-compare-debug-2.c: ... this.  Add -O2.
2020-03-29 00:06:54 +03:00
Paul Thomas
7d57570b06 Patch for PR94246 2020-03-28 19:11:35 +00:00
Tobias Burnus
3fb7f2fbd5 [Fortran] Fix result-variable handling of MODULE PROCEDURE (PR94348)
PR fortran/94348
	* decl.c (gfc_match_submod_proc): Add result var to the
	proc's namespace.

	PR fortran/94348
	* gfortran.dg/module_procedure_3.f90: New.
2020-03-28 14:01:57 +01:00
Patrick Palka
7981c06ae9 c++: Diagnose when "requires" is used instead of "requires requires" [PR94306]
This adds support to detect and recover from the case where an opening brace
immediately follows the start of a requires-clause.  So rather than emitting the
error

  error: expected primary-expression before '{' token

followed by a slew of irrevelant errors, we now assume the user had intended to
write "requires requires {" and diagnose and recover accordingly.

gcc/cp/ChangeLog:

	PR c++/94306
	* parser.c (cp_parser_requires_clause_opt): Diagnose and recover from
	"requires {" when "requires requires {" was probably intended.

gcc/testsuite/ChangeLog:

	PR c++/94306
	* g++.dg/concepts/diagnostic8.C: New test.
2020-03-28 08:57:11 -04:00
Patrick Palka
a7ea3d2ced c++: requires-expression outside of a template is misevaluated [PR94252]
This PR shows that a REQUIRES_EXPR outside of a template can sometimes be
misevaluated.  This happens because the evaluation routine tsubst_requires_expr
(and diagnose_requires_expr) assumes the REQUIRES_EXPR's subtrees are templated
trees and that therefore it's safe to call tsubst_expr on them.  But this
assumption isn't valid when we've parsed a REQUIRES_EXPR outside of a template
context.  In order to make this assumption valid here, this patch sets
processing_template_decl to non-zero before parsing the body of a REQUIRES_EXPR
so that its subtrees are indeed always templated trees.

gcc/cp/ChangeLog:

	PR c++/94252
	* constraint.cc (tsubst_compound_requirement): Always suppress errors
	from type_deducible_p and expression_convertible_p, as they're not
	substitution errors.
	(diagnose_atomic_constraint) <case INTEGER_CST>: Remove this case so
	that we diagnose INTEGER_CST expressions of non-bool type via the
	default case.
	* cp-gimplify.c (cp_genericize_r) <case REQUIRES_EXPR>: New case.
	* parser.c (cp_parser_requires_expression): Always parse the requirement
	body as if we're processing a template, by temporarily incrementing
	processing_template_decl.  Afterwards, if we're not actually in a
	template context, perform semantic processing to diagnose any invalid
	types and expressions.
	* pt.c (tsubst_copy_and_build) <case REQUIRES_EXPR>: Remove dead code.
	* semantics.c (finish_static_assert): Explain an assertion failure
	when the condition is a REQUIRES_EXPR like we do when it is a concept
	check.

gcc/testsuite/ChangeLog:

	PR c++/94252
	* g++.dg/concepts/diagnostic7.C: New test.
	* g++.dg/concepts/pr94252.C: New test.
	* g++.dg/cpp2a/concepts-requires18.C: Adjust to expect an additional
	diagnostic.
2020-03-28 08:56:59 -04:00
Patrick Palka
cd68edf894 c++: Respect current_constraint_diagnosis_depth in diagnose_compound_requirement
The previous patch tries to avoid changing our current default diagnostics.  But
for the sake of consistency we arguably should also respect
current_constraint_diagnosis_depth in diagnose_compound_requirement() like we do
in the other error-replaying diagnostic routines.  But doing so would be a
change to our default diagnostics behavior, so the change has been split out
into this separate patch for separate consideration.

gcc/cp/ChangeLog:

	* constraint.cc (diagnose_compound_requirement): When diagnosing a
	compound requirement, maybe replay the satisfaction failure, subject to
	the current diagnosis depth.

gcc/testsuite/ChangeLog:

	* g++.dg/concepts/diagnostic1.C: Pass -fconcepts-diagnostics-depth=2.
	* g++.dg/concepts/diagnostic5.C: Adjust expected diagnostics.
	* g++.dg/cpp2a/concepts-iconv1.C: Pass -fconcepts-diagnostics-depth=2.
	* g++.dg/cpp2a/concepts-requires5.C: Likewise.
2020-03-28 08:56:33 -04:00
Patrick Palka
75defde9fb c++: Replay errors during diagnosis of constraint satisfaction failures
This patch adds a new flag -fconcepts-diagnostics-depth to the C++ frontend
which controls how deeply we replay errors when diagnosing a constraint
satisfaction failure.  The default is -fconcepts-diagnostics-depth=1 which
diagnoses only the topmost constraint satisfaction failure and is consistent
with our behavior before this patch.  By increasing this flag's value, the user
can control how deeply they want the compiler to explain a constraint
satisfaction error.

For example, if the unsatisfied constraint is a disjunction, then the default
behavior is to just say "no branch in the disjunction is satisfied", but with
-fconcepts-diagnostics-depth=2 we will additionally replay and diagnose the
error in each branch of the disjunction.  And if the unsatisfied constraint is a
requires expression, then we will replay the error in the requires expression,
etc.  This proceeds recursively until there is nothing more to replay or we
exceeded the maximum depth specified by the flag.

Implementation wise, this patch essentially just uncomments the existing
commented-out code that performs the error-replaying, and along the way adds
logic to keep track of and limit the current replay depth.  Besides that, there
is a new routine collect_operands_of_disjunction which flattens a disjunction
and collects all of its operands into a vector.

The extra diagnostics enabled by this flag are at times longer than they need to
be (e.g.  "the operand is_array_v<...> is unsatisfied because \n the expression
is_array_v<...> [with ...] evaluated to false") and not immediately easy to
follow (especially when there are nested disjunctions), but the transparency
provided by these optional diagnostics seems to be pretty helpful in practice.

gcc/c-family/ChangeLog:

	* c.opt: Add -fconcepts-diagnostics-depth.

gcc/cp/ChangeLog:

	* constraint.cc (finish_constraint_binary_op): Set the location of EXPR
	as well as its range, because build_x_binary_op doesn't always do so.
	(current_constraint_diagnosis_depth): New.
	(concepts_diagnostics_max_depth_exceeded_p): New.
	(collect_operands_of_disjunction): New.
	(satisfy_disjunction): When diagnosing a satisfaction failure, maybe
	replay each branch of the disjunction, subject to the current diagnosis
	depth.
	(diagnose_valid_expression): When diagnosing a satisfaction failure,
	maybe replay the substitution error, subject to the current diagnosis
	recursion.
	(diagnose_valid_type): Likewise.
	(diagnose_nested_requiremnet): Likewise.
	(diagnosing_failed_constraint::diagnosing_failed_constraint): Increment
	current_constraint_diagnosis_depth when diagnosing.
	(diagnosing_failed_constraint::~diagnosing_failed_constraint): Decrement
	current_constraint_diagnosis_depth when diagnosing.
	(diagnosing_failed_constraint::replay_errors_p): New static member
	function.
	(diagnose_constraints): Don't diagnose if concepts_diagnostics_max_depth
	is 0.  Emit a one-off note to increase -fconcepts-diagnostics-depth if
	the limit was exceeded.
	* cp-tree.h (diagnosing_failed_constraint::replay_errors_p): Declare.

gcc/testsuite/ChangeLog:

	* g++.dg/concepts/diagnostic2.C: Expect "no operand" instead of
	"neither operand".
	* g++.dg/concepts/diagnostic5.C: New test.
2020-03-28 08:43:20 -04:00
Jakub Jelinek
c6a562de88 c: After issuing errors about array size, for error-recovery don't make the array VLA [PR93573]
After we report various errors about array size, we set for error-recovery
the size to be 1, but because size_int_const is false, it still means we
pretend the array is a VLA, can emit a second diagnostics in that case etc.
E.g.
$ ./cc1.unpatched -quiet a.c
a.c:1:5: error: size of array ‘f’ has non-integer type
    1 | int f[100.0];
      |     ^
a.c:1:1: warning: variably modified ‘f’ at file scope
    1 | int f[100.0];
      | ^~~
$ ./cc1 -quiet a.c
a.c:1:5: error: size of array ‘f’ has non-integer type
    1 | int f[100.0];
      |     ^

2020-03-28  Jakub Jelinek  <jakub@redhat.com>

	PR c/93573
	* c-decl.c (grokdeclarator): After issuing errors, set size_int_const
	to true after setting size to integer_one_node.

	* gcc.dg/pr93573-1.c: New test.
	* gcc.dg/pr93573-2.c: New test.
2020-03-28 10:30:31 +01:00
Jakub Jelinek
679becf175 reassoc: Fix -fcompare-debug bug in reassociate_bb [PR94329]
The following testcase FAILs with -fcompare-debug, because reassociate_bb
mishandles the case when the last stmt in a bb has zero uses.  In that case
reassoc_remove_stmt (like gsi_remove) moves the iterator to the next stmt,
i.e. gsi_end_p is true, which means the code sets the iterator back to
gsi_last_bb.  The problem is that the for loop does gsi_prev on that before
handling the next statement, which means the former penultimate stmt, now
last one, is not processed by reassociate_bb.
Now, with -g, if there is at least one debug stmt at the end of the bb,
reassoc_remove_stmt moves the iterator to that following debug stmt and we
just do gsi_prev and continue with the former penultimate non-debug stmt,
now last non-debug stmt.

The following patch fixes that by not doing the gsi_prev in this case; there
are too many continue; cases, so I didn't want to copy over the gsi_prev to
all of them, so this patch uses a bool for that instead.  The second
gsi_end_p check isn't needed anymore, because when we don't do the
undesirable gsi_prev after gsi = gsi_last_bb, the loop !gsi_end_p (gsi)
condition will catch the removal of the very last stmt from a bb.

2020-03-28  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/94329
	* tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
	on the last stmt in a bb, make sure gsi_prev isn't done immediately
	after gsi_last_bb.

	* gfortran.dg/pr94329.f90: New test.
2020-03-28 10:21:52 +01:00
GCC Administrator
c278119229 Daily bump. 2020-03-28 00:16:20 +00:00
Jonathan Wakely
b8a28a06ea libstdc++: Define __cpp_lib_ranges macro for C++20
Define the feature test macro now that ranges support is complete.

This also changes the preprocessor checks for the __cpp_concepts macro
so that library components depending on concepts are only enabled when
C++20 concepts are supported, and not just for the Concepts TS (which
uses different syntax in places).

	* include/bits/range_cmp.h (__cpp_lib_ranges): Define.
	* include/bits/stl_iterator.h: Check value of __cpp_concepts so that
	C++20 concepts are required.
	* include/bits/stl_iterator_base_types.h: Likewise.
	* include/std/concepts: Likewise.
	* include/std/version: Likewise.
	* testsuite/std/ranges/headers/ranges/synopsis.cc: Check feature test
	macro.
2020-03-27 23:26:03 +00:00
Jonathan Wakely
81a8d137c2 libstdc++: Add remaining C++20 changes to iterator adaptors
This adds the missing parts of P0896R4 to reverse_iterator and
move_iterator, so that they meet the C++20 requirements. This should be
the last piece of P0896R4, meaning ranges support is now complete.

The PR 94354 bug with reverse_iterator's comparisons is fixed for C++20
only, but that change should be extended to C++11, C++14 and C++17 modes
in stage 1.

	* include/bits/stl_iterator.h (reverse_iterator::iterator_concept)
	(reverse_iterator::iterator_category): Define for C++20.
	(reverse_iterator): Define comparison operators correctly for C++20.
	(__normal_iterator): Add constraints to comparison operators for C++20.
	(move_iterator::operator++(int)) [__cpp_lib_concepts]: Define new
	overload for input iterators.
	(move_iterator): Add constraints to comparison operators for C++20.
	Define operator<=> for C++20.
	* testsuite/24_iterators/move_iterator/input_iterator.cc: New test.
	* testsuite/24_iterators/move_iterator/move_only.cc: New test.
	* testsuite/24_iterators/move_iterator/rel_ops_c++20.cc: New test.
	* testsuite/24_iterators/reverse_iterator/rel_ops_c++20.cc: New test.
2020-03-27 23:26:03 +00:00
Jonathan Wakely
ae6076b5bc libstdc++: Implement C++20 changes to insert iterators
std::insert_iterator and std::inserter need to be adjusted for C++20, so
that they use ranges::iterator_t. That alias template requires
ranges::begin to be defined. Rather than moving the whole of
ranges::begin (and related details like ranges::enable_borrowed_range)
into <iterator>, this defines a new, simpler version of ranges::begin
that is sufficient for ranges::iterator_t to be defined. This works
because ranges::iterator_t uses an lvalue reference type, so the logic
in ranges::begin for non-lvalue ranges (i.e. borrowed ranges) isn't
needed.

This also adds the missing constexpr specifiers to the other insert
iterators.

	* include/bits/iterator_concepts.h (__detail::__decay_copy)
	(__detail::__member_begin, __detail::__adl_begin): Move here from
	<bits/range_access.h>.
	(__detail::__ranges_begin, __detail::__range_iter_t): Define.
	* bits/range_access.h (__cust_access::__decay_copy)
	(__cust_access::__member_begin, __cust_access::__adl_begin): Move to
	<bits/iterator_concepts.h>.
	(ranges::iterator_t): Use __detail::__range_iter_t.
	* include/bits/stl_iterator.h (back_insert_iterator): Simplify
	conditional compilation. Add _GLIBCXX20_CONSTEXPR to all members.
	(front_insert_iterator): Likewise.
	(insert_iterator): Implement changes from P0896R4 for C++20.
	* testsuite/24_iterators/back_insert_iterator/constexpr.cc: New test.
	* testsuite/24_iterators/front_insert_iterator/constexpr.cc: New test.
	* testsuite/24_iterators/headers/iterator/synopsis_c++17.cc: Adjust
	for inclusion in synopsis_c++20.cc which expects different signatures
	for some function templates.
	* testsuite/24_iterators/insert_iterator/constexpr.cc: New test.
2020-03-27 23:26:01 +00:00
Jonathan Wakely
0302a2de7f libstdc++: Move definition earlier in file
This moves __is_array_convertible so it's not between
__is_nothrow_convertible and its helper, since it isn't related to
those.

	* include/std/type_traits (__is_array_convertible): Move definition
	to immediately after is_convertible.
2020-03-27 22:53:04 +00:00
Joseph Myers
491009b609 Update gcc de.po. 2020-03-27 22:34:08 +00:00
Alan Modra
19e5389deb [RS6000] PR94145, make PLT loads volatile
The PLT is volatile.  On PowerPC it is a bss style section which the
dynamic loader initialises to point at resolver stubs (called glink on
PowerPC64) to support lazy resolution of function addresses.  The
first call to a given function goes via the dynamic loader symbol
resolver, which updates the PLT entry for that function and calls the
function.  The second call, if there is one and we don't have a
multi-threaded race, will use the updated PLT entry and thus avoid
the relatively slow symbol resolver path.

Calls via the PLT are like calls via a function pointer, except that
no initialised function pointer is volatile like the PLT.  All
initialised function pointers are resolved at program startup to point
at the function or are left as NULL.  There is no support for lazy
resolution of any user visible function pointer.

So why does any of this matter to gcc?  Well, normally the PLT call
mechanism happens entirely behind gcc's back, but since we implemented
inline PLT calls (effectively putting the PLT code stub that loads the
PLT entry inline and making that code sequence scheduled), the load of
the PLT entry is visible to gcc.  That load then is subject to gcc
optimization, for example in

/* -S -mcpu=future -mpcrel -mlongcall -O2.  */
int foo (int);
void bar (void)
{
  while (foo(0))
    foo (99);
}

we see the PLT load for foo being hoisted out of the loop and stashed
in a call-saved register.  If that happens to be the first call to
foo, then the stashed value is that for the resolver stub, and every
call to foo in the loop will then go via the slow resolver path.  Not
a good idea.  Also, if foo turns out to be a local function and the
linker replaces the PLT calls with direct calls to foo then gcc has
just wasted a call-saved register.

This patch teaches gcc that the PLT loads are volatile.  The change
doesn't affect other loads of function pointers and thus has no effect
on normal indirect function calls.  Note that because the
"optimization" this patch prevents can only occur over function calls,
the only place gcc can stash PLT loads is in call-saved registers or
in other memory.  I'm reasonably confident that this change will be
neutral or positive for the "ld -z now" case where the PLT is not
volatile, in code where there is any register pressure.  Even if gcc
could be taught to recognise cases where the PLT is resolved, you'd
need to discount use of registers to cache PLT loads by some factor
involving the chance that those calls would be converted to direct
calls.

	PR target/94145
	* config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
	for PLT16_LO and PLT_PCREL.
	* config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
	(UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
	(pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
2020-03-28 08:22:37 +10:30
Jakub Jelinek
54de5afb4a c++: Handle COMPOUND_EXPRs in ocp_convert [PR94339]
With the PR94346 fix in, we can revert the attr-copy-2.C workaround.

2020-03-27  Jakub Jelinek  <jakub@redhat.com>

	PR c++/94339
	* g++.dg/ext/attr-copy-2.C: Revert the last changes.
2020-03-27 22:29:50 +01:00
Martin Sebor
52f24a9e98 PR c++/94346 - [9/10 Regression] ICE due to handle_copy_attribute since r9-3982
gcc/c-family/ChangeLog:

	PR c++/94346
	* c-attribs.c (handle_copy_attribute): Avoid passing expressions
	to decl_attributes.  Make handling of different kinds of entities
	more robust.

gcc/c-c++-common/ChangeLog:

	PR c++/94346
	* c-c++-common/attr-copy.c: New test.
2020-03-27 14:33:57 -06:00
Nathan Sidwell
c7fc15f54b [pr84733] Fix ICE popping local scope
PR c++/84733
	* name-lookup.c (do_pushdecl): Look through cleanp levels.
2020-03-27 13:09:12 -07:00