Commit graph

208536 commits

Author SHA1 Message Date
David Malcolm
d5604febcf analyzer: fix ICE on strlen ((char *)&VECTOR_CST) [PR111361]
gcc/analyzer/ChangeLog:
	PR analyzer/111361
	* region-model.cc (svalue_byte_range_has_null_terminator_1): The
	initial byte of an all-zeroes SVAL is a zero byte.  Remove
	gcc_unreachable from SK_CONSTANT for constants that aren't
	STRING_CST or INTEGER_CST.

gcc/testsuite/ChangeLog:
	PR analyzer/111361
	* c-c++-common/analyzer/strlen-pr111361.c: New test.
	* c-c++-common/analyzer/strncpy-1.c (test_zero_fill): Remove fixed
	xfail.
	* c-c++-common/analyzer/strncpy-pr111361.c: New test.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-01-18 12:11:57 -05:00
David Malcolm
84096e665c analyzer: fix offsets in has_null_terminator [PR112811]
PR analyzer/112811 reports an ICE attempting to determine whether a
string is null-terminated.

The root cause is confusion in the code about whether byte offsets are
relative to the start of the base region, or relative to the bound
fragment within the the region.

This patch rewrites the code to enforce a clearer separation between
the kinds of offset, fixing the ICE, and adds logging to help track
down future issues in this area of the code.

gcc/analyzer/ChangeLog:
	PR analyzer/112811
	* region-model.cc (fragment::dump_to_pp): New.
	(fragment::has_null_terminator): Convert to...
	(svalue_byte_range_has_null_terminator_1): ...this new function,
	updating to use a byte_range relative to the start of the svalue.
	(svalue_byte_range_has_null_terminator): New.
	(fragment::string_cst_has_null_terminator): Convert to...
	(string_cst_has_null_terminator): ...this, updating to use a
	byte_range relative to the start of the svalue.
	(iterable_cluster::dump_to_pp): New.
	(region_model::scan_for_null_terminator): Add logging, moving body
	to...
	(region_model::scan_for_null_terminator_1): ...this new function,
	adding more logging, and updating to use
	svalue_byte_range_has_null_terminator.
	* region-model.h (region_model::scan_for_null_terminator_1): New
	decl.

gcc/testsuite/ChangeLog:
	PR analyzer/112811
	* c-c++-common/analyzer/strlen-pr112811.c: New test.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-01-18 12:11:57 -05:00
David Malcolm
e254d1224d Fix ICE in -fdiagnostics-generate-patch [PR112684]
gcc/ChangeLog:
	PR middle-end/112684
	* toplev.cc (toplev::main): Don't ICE in
	-fdiagnostics-generate-patch when exiting after options,
	since no edit context will have been created.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-01-18 12:11:57 -05:00
Patrick Palka
8cddf6f833 libstdc++/pair: Guard P2321R2 changes with __glibcxx_ranges_zip
Similar to the previous change for <tuple>, but since stl_pair.h is an
internal header we need to use the corresponding internal macro instead.

libstdc++-v3/ChangeLog:

	* include/bits/stl_pair.h [__cplusplus > 202002L]:
	Guard P2321R2 changes with __glibcxx_ranges_zip instead.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
2024-01-18 11:21:34 -05:00
Patrick Palka
ae8581ea5c libstdc++/tuple: Guard P2321R2 changes with __cpp_lib_ranges_zip
Guard <tuple> additions from P2321R2 zip with __cpp_lib_ranges_zip
instead of __cplusplus > 202020L.

libstdc++-v3/ChangeLog:

	* include/std/tuple [__cplusplus > 202002L]: Guard P2321R2
	changes with __cpp_lib_ranges_zip instead.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
2024-01-18 11:21:16 -05:00
Patrick Palka
3d3145e9e1 libstdc++/debug: Fix constexpr _Safe_iterator in C++20 mode [PR109536]
Some _Safe_iterator member functions define a variable of non-literal
type __gnu_cxx::__scoped_lock, which automatically disqualifies them from
being constexpr in C++20 mode even if that code path is never constant
evaluated.  This restriction was lifted by P2242R3 for C++23, but we
need to work around it in C++20 mode.  To that end this patch defines
a pair of macros that encapsulate the lambda-based workaround mentioned
in that paper and uses it to make these functions valid C++20 constexpr
functions.  The augmented std::vector test element_access/constexpr.cc
now successfully compiles in C++20 mode with -D_GLIBCXX_DEBUG (and it
should test all member functions modified by this patch).

	PR libstdc++/109536

libstdc++-v3/ChangeLog:

	* include/debug/safe_base.h (_Safe_sequence_base::_M_swap):
	Remove _GLIBCXX20_CONSTEXPR from non-inline member function.
	* include/debug/safe_iterator.h
	(_GLIBCXX20_CONSTEXPR_NON_LITERAL_SCOPE_BEGIN): Define.
	(_GLIBCXX20_CONSTEXPR_NON_LITERAL_SCOPE_END): Define.
	(_Safe_iterator::operator=): Use them around the code path that
	defines a variable of type __gnu_cxx::__scoped_lock.
	(_Safe_iterator::operator++): Likewise.
	(_Safe_iterator::operator--): Likewise.
	(_Safe_iterator::operator+=): Likewise.
	(_Safe_iterator::operator-=): Likewise.
	* testsuite/23_containers/vector/element_access/constexpr.cc
	(test_iterators): Test more iterator operations.
	* testsuite/23_containers/vector/bool/element_access/constexpr.cc
	(test_iterators): Likewise.
	* testsuite/std/ranges/adaptors/all.cc (test08) [_GLIBCXX_DEBUG]:
	Remove.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
2024-01-18 10:36:07 -05:00
H.J. Lu
48c8d26d77 hwasan: Always set target_hwasan_flags
Fix the "make check" error:

Running .../gcc/testsuite/gcc.dg/hwasan/hwasan.exp ...
ERROR: tcl error sourcing .../gcc/testsuite/gcc.dg/hwasan/hwasan.exp.
ERROR: tcl error code TCL LOOKUP VARNAME target_hwasan_flags
ERROR: can't read "target_hwasan_flags": no such variable
...

on non-x86-64 targets.

	* lib/hwasan-dg.exp (hwasan_init): Always set target_hwasan_flags.
2024-01-18 07:14:16 -08:00
Richard Biener
d190a5553a Another memory leak in vectorizable_store
Similar to the last one.

	* tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
	operands vector.
2024-01-18 16:07:34 +01:00
Iain Sandoe
569ebd6bdd Darwin, configure: Handle a missing substitution.
The configure substitution for enable_darwin_at_rpath has been
omitted, which leads to a failure to set ENABLE_DARWIN_AT_RPATH in
the testsuite site.exp (which leads to failure to add -B options
in some cases, breaking uninstalled testing there).

Since we already have substitutions for ENABLE_DARWIN_AT_RPATH_TRUE
we can use that instead, which is what this patch does.

gcc/ChangeLog:

	* Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
	when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 15:03:26 +00:00
Jun Sha (Joshua)
9e1b554cc7 RISC-V: Rewrite some instructions using ASM targethook
There are some xtheadvector instructions that differ from RVV1.0
apart from simply adding "th." prefix. For example, RVV1.0
load/store instructions will have SEW while xtheadvector not;
RVV1.0 will have "o" for indexed-ordered store instructions while
xtheadvecotr not; xtheadvector and RVV1.0 have different
vnsrl/vnsra/vfncvt suffix (vv/vx/vi vs wv/wx/wi).

To address this issue without duplicating patterns, we use ASM
targethook to rewrite the whole string of the instructions. We
identify different instructions from the corresponding attribute.

gcc/ChangeLog:

	* config/riscv/thead.cc
	(th_asm_output_opcode): Rewrite some instructions.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-01-18 15:40:07 +01:00
Jun Sha (Joshua)
cdf4729f08 RISC-V: Fix register overlap issue for some xtheadvector instructions
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.

To handle this issue, we add an attribute "spec_restriction" to disable
some alternatives for xtheadvector.

gcc/ChangeLog:

	* config/riscv/riscv.md (none,thv,rvv): New attribute.
	(no,yes): Add an attribute to disable alternative
	for xtheadvector or RVV1.0.
	* config/riscv/vector.md:
	Disable alternatives that destination register overlaps
	source register group for xtheadvector.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-01-18 15:39:52 +01:00
Jun Sha (Joshua)
0a41c3e49a RISC-V: Add support for xtheadvector-specific intrinsics.
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class th_loadstore_width): Define new builtin bases.
	(class th_extract): Define new builtin bases.
	(BASE): Define new builtin bases.
	* config/riscv/riscv-vector-builtins-bases.h:
	Define new builtin class.
	* config/riscv/riscv-vector-builtins-shapes.cc
	(struct th_loadstore_width_def): Define new builtin shapes.
	(struct th_indexed_loadstore_width_def):
	Define new builtin shapes.
	(struct th_extract_def): Define new builtin shapes.
	(SHAPE): Define new builtin shapes.
	* config/riscv/riscv-vector-builtins-shapes.h:
	Define new builtin shapes.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
	Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
	* config/riscv/riscv-vector-builtins.h
	(enum required_ext): Add new XTheadVector member.
	(struct function_group_info): Likewise.
	* config/riscv/t-riscv:
	Add thead-vector-builtins-functions.def
	* config/riscv/thead-vector.md
	(@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
	(*pred_mov_width<vlmem_op_attr><mode>): Likewise.
	(@pred_store_width<vlmem_op_attr><mode>): Likewise.
	(@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
	(@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
	(@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
	(@pred_th_extract<mode>): Likewise.
	(*pred_th_extract<mode>): Likewise.
	* config/riscv/thead-vector-builtins-functions.def: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
	* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
	* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
	* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
	* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
	* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-01-18 15:38:45 +01:00
Jun Sha (Joshua)
2d7205eb2c RISC-V: Handle differences between XTheadvector and Vector
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches.

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r.

gcc/ChangeLog:

	* config.gcc:  Add files for XTheadVector intrinsics.
	* config/riscv/autovec.md: Guard XTheadVector.
	* config/riscv/predicates.md: Disable immediate vl
	for XTheadVector.
	* config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
	Add pragma for XTheadVector.
	* config/riscv/riscv-string.cc (riscv_expand_block_move):
	Guard XTheadVector.
	* config/riscv/riscv-v.cc (vls_mode_valid_p):
	Avoid autovec.
	* config/riscv/riscv-vector-builtins-bases.cc:
	Do not normalize vsetvl instructions for XTheadVector.
	* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
	New check type function.
	(build_one): Adjust for XTheadVector.
	* config/riscv/riscv-vector-switch.def (ENTRY):
	Disable fractional mode for the XTheadVector extension.
	(TUPLE_ENTRY): Likewise.
	* config/riscv/riscv.cc (riscv_v_adjust_bytesize):
	Guard XTheadVector.
	(riscv_preferred_simd_mode): Likewsie.
	(riscv_autovectorize_vector_modes): Likewise.
	(riscv_vector_mode_supported_any_target_p): Likewise.
	(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
	* config/riscv/thead.cc (th_asm_output_opcode):
	Rewrite vsetvl instructions.
	* config/riscv/vector.md:
	Include thead-vector.md and change fractional LMUL
	into 1 for vbool.
	* config/riscv/riscv_th_vector.h: New file.
	* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
	* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
	* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-01-18 15:38:35 +01:00
Jun Sha (Joshua)
9a55cc625c RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
	Add new function to add assembler insn code prefix/suffix.
	(th_asm_output_opcode):
	Add Thead function to add assembler insn code prefix/suffix.
	* config/riscv/riscv.cc (riscv_asm_output_opcode):
	Implement function to add assembler insn code prefix/suffix.
	* config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
	Add new function to add assembler insn code prefix/suffix.
	* config/riscv/thead.cc (th_asm_output_opcode):
	Implement Thead function to add assembler insn code
	prefix/suffix.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xtheadvector/prefix.c: New test.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-01-18 15:32:49 +01:00
Jun Sha (Joshua)
d05b526511 RISC-V: Introduce XTheadVector as a subset of V1.0.0
This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc
	(riscv_subset_list::parse): Add new vendor extension.
	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
	Add test marco.
	* config/riscv/riscv.opt:  Add new mask.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
	* gcc.target/riscv/rvv/xtheadvector.c: New test.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-01-18 15:32:49 +01:00
Iain Sandoe
60f58d0630 Objective-C/C++: Ensure sufficient setup for the preprocessor.
The tokenizer makes use of functions that determine if identifiers
are interface or class names, and those functions need a hash map
to be set up.

This ensures that these are initialized before pre-process-only
jobs are run.

gcc/objc/ChangeLog:

	* objc-act.cc (objc_init): Initialize interface and class
	name hash maps before the preprocessor uses them.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 14:27:54 +00:00
Iain Sandoe
49478485f2 Darwin: Suppress adding embedded rpaths for earlier OS versions.
When we have @rpath support by virtue of the OS version we're hosting on
we still need to omit those rpath entries when targeting < 10.5 (or the
linker will complain).  To do this we (maybe ab-)use a property of the
spec function expansion that a non-null return value can be used as the
true input to a second spec (whereas, unfortunately, we cannot pass specs
to the version function at present).

gcc/ChangeLog:

	* config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
	to be conditional on macosx-version-min.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 14:22:16 +00:00
Iain Sandoe
8d26636f0d Darwin: Fix a typo in Objective-C meta-data.
We have a typo in the metadata for assigning NSStrings to a specific
section for the V1 (32b) ABI.  When that is fixed we should never see
the case where the section needs to be deduced from the properties of
the DECLs.

gcc/ChangeLog:

	* config/darwin.cc (darwin_objc1_section): Use the correct
	meta-data version for constant strings.
	(machopic_select_section): Assert if we fail to handle CFString
	sections as Obejctive-C meta-data or drectly.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 14:15:55 +00:00
Marek Polacek
9840e0be78 c++: ICE when xobj is not the first parm [PR113389]
In grokdeclarator/cdk_function the comment says that the find_xobj_parm
lambda clears TREE_PURPOSE so that we can correctly detect an xobj that
is not the first parameter.  That's all good, but we should also clear
the TREE_PURPOSE once we've given the error, otherwise we crash later in
check_default_argument because the 'this' TREE_PURPOSE lacks a type.

	PR c++/113389

gcc/cp/ChangeLog:

	* decl.cc (grokdeclarator) <case cdk_function>: Set TREE_PURPOSE to
	NULL_TREE when emitting an error.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp23/explicit-obj-diagnostics10.C: New test.
2024-01-18 09:11:57 -05:00
Iain Sandoe
1d82a2d933 lto, Darwin: Fix offload section names.
Currently, these section names have wrong syntax for Mach-O.
Although they were added some time ago; recently added tests are
now emitting them leading to new fails on Darwin.

This adds a Mach-O variant for each.

gcc/ChangeLog:

	* lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
	OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
	OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
	versions when the object format is Mach-O.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 14:02:19 +00:00
Iain Sandoe
efe4ea2754 testsuite, jit, Darwin: Add libSystem to a test.
test-ggc-bugfix.c fails early on Darwin versions using a linker that
complains if libSystem is not present on user-land link lines.

Add this to fix that specific issue.

gcc/testsuite/ChangeLog:

	* jit.dg/test-ggc-bugfix.c: Add libSystem for Darwin.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 14:01:45 +00:00
Iain Sandoe
283e3a974b testsuite, jit, Darwin: Handle Mach-O in assembler tests.
Several of the jit tests check for assembler-specific output
which differs on Mach-O from ELF.

This patch uses the facility to make the scans target-dependent
and adds handling for darwin.

gcc/testsuite/ChangeLog:

	* jit.dg/test-always_inline-attribute.c: Handle Darwin in
	jit-verify-assembler-output.
	* jit.dg/test-noinline-attribute.c: Likewise.
	* jit.dg/test-setting-alignment.c: Likewise.
	* jit.dg/test-used-attribute.c: Likewise.
	* jit.dg/test-variable-attribute.c: Likewise.
	* jit.dg/test-weak-attribute.c: Likewise.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 14:01:21 +00:00
Iain Sandoe
e0e3ef18a0 testsuite, jit: Allow for target-specific assembler scans.
If we want to support multiple object formats and to allow for
scan-assembler tests, we need to make it possible to adjust the
tests on a per-target basis.

This adds similar mechamisms to jit-verify-assembler-output{,-not}
to those used for the general scan-assembler dg directives.

As an aside; it would, perhaps, be possible to integrate this more
with scanasm.exp (which would also give access to function body
scanning) but I did not attempt that for this patch.

After this, we can accept things like:
... { jit-verify-assembler-output-not "......" { target { ! *-*-darwin* } } } }
or
... { jit-verify-assembler-output "......" { target *-*-darwin* } } }

gcc/testsuite/ChangeLog:

	* jit.dg/jit.exp: Accept target clauses in jit-verify-assembler
	handling.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 14:00:58 +00:00
Iain Sandoe
2b0abfd3f8 testsuite, jit: Handle whitespace in test-link-section-assembler.c.
Darwin has a different .section directive that has more fields and
uses different whitespace.  Amend the whitespace in the scan-asm to
be more flexible.

gcc/testsuite/ChangeLog:

	* jit.dg/test-link-section-assembler.c: Accept any whitespace
	between the .section directive and its arguments.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 14:00:36 +00:00
Iain Sandoe
ea9df9085a testsuite, jit: test-alias-attribute.c requires alias support.
Add a dg-require-alias to cover this.

gcc/testsuite/ChangeLog:

	* jit.dg/test-alias-attribute.c: Require target alias
	support.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 14:00:11 +00:00
Iain Sandoe
aecc0d4ba7 Darwin: Fix constant CFString code-gen [PR105522].
Although this only fires for one of the Darwin sub-ports, it is latent
elsewhere, it is also a regression c.f. the Darwin system compiler.

In the code we imported from an earlier branch, CFString objects (which
are constant aggregates) are constructed as CONST_DECLs.  Although our
current documentation suggests that these are reserved for enumeration
values, in fact they are used elsewhere in the compiler for constants.
This includes Objective-C where they are used to form NSString constants.

In the particular case, we take the address of the constant and that
triggers varasm.cc:decode_addr_constant, which does not currently support
CONST_DECL.

If there is a general intent to allow/encourage wider use of CONST_DECL,
then we should fix decode_addr_constant to look through these and evaluate
the initializer (a two-line patch, but I'm not suggesting it for stage-4).

We also need to update the GCC internals documentation to allow for the
additional uses.

This patch is Darwin-local and fixes the problem by making the CFString
constants into regular variable but TREE_CONSTANT+TREE_READONLY. I plan
to back-port this to the open branches once it has baked a while on trunk.

Since, for Darwin, the Objective-C default is to construct constant
NSString objects as CFStrings; this will also cover the majority of cases
there (this patch does not make any changes to Objective-C NSStrings).

	PR target/105522

gcc/ChangeLog:

	* config/darwin.cc (machopic_select_section): Handle C and C++
	CFStrings.
	(darwin_rename_builtins): Move this out of the CFString code.
	(darwin_libc_has_function): Likewise.
	(darwin_build_constant_cfstring): Create an anonymous var to
	hold each CFString.
	* config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
	CFstrings.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-01-18 13:54:17 +00:00
Maxim Kuvyrkov
a6bf09f65a Fix compare-debug bootstrap failure [PR113445]
... caused by scheduler fix for PR96388 and PR111554.

This patch adjusts decision sched-deps.cc:find_inc() to use
length of dependency lists sans any DEBUG_INSN instructions.

gcc/ChangeLog

2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>

	PR bootstrap/113445
	* haifa-sched.cc (dep_list_size): Make global.
	* sched-deps.cc (find_inc): Use instead of sd_lists_size().
	* sched-int.h (dep_list_size): Declare.

gcc/testsuite/ChangeLog

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

	PR bootstrap/113445
	* gcc.dg/pr113445.c: New test.
2024-01-18 14:45:27 +01:00
Martin Jambor
6764043e88
sra: Disqualify bases of operands of asm gotos
PR 110422 shows that SRA can ICE assuming there is a single edge
outgoing from a block terminated with an asm goto.  We need that for
BB-terminating statements so that any adjustments they make to the
aggregates can be copied over to their replacements.  Because we can't
have that after ASM gotos, we need to punt.

gcc/ChangeLog:

2024-01-17  Martin Jambor  <mjambor@suse.cz>

	PR tree-optimization/110422
	* tree-sra.cc (scan_function): Disqualify bases of operands of asm
	gotos.

gcc/testsuite/ChangeLog:

2024-01-17  Martin Jambor  <mjambor@suse.cz>

	PR tree-optimization/110422
	* gcc.dg/torture/pr110422.c: New test.
2024-01-18 14:25:30 +01:00
Richard Biener
895a213826 tree-optimization/113475 - fix memory leak in phi_analyzer
phi_analyzer leaks all phi_group objects it allocates.  The following
fixes this by maintaining a vector of allocated objects and release
them when destroying the phi_analyzer object.

	PR tree-optimization/113475
	* gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
	* gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
	(phi_analyzer::~phi_analyzer): Deallocate and free collected
	phi_grous.
	(phi_analyzer::process_phi): Record allocated phi_groups.
2024-01-18 14:13:03 +01:00
Richard Biener
5b421c2a5b Fix memory leak in vectorizable_store
The following fixes a memory leak in vectorizable_store which happens
because the functions populating gvec_oprnds[i] will call .create ()
on the incoming vector, leaking what we've previously allocated.

	* tree-vect-stmts.cc (vectorizable_store): Do not allocate
	storage for gvec_oprnds elements.
2024-01-18 14:13:03 +01:00
Gaius Mulley
f2872e00f6 PR modula2/111956 Many powerpc platforms do _not_ have support for IEEE754
This patch corrects commit
r14-4149-g81d5ca0b9b8431f1bd7a5ec8a2c94f04bb0cf032 which assummed
all powerpc platforms would have IEEE754 long double.  The patch
ensures that cc1gm2 obtains the default IEEE754 long double availability
from the configure generated tm_defines.  The user command
line switches -mabi=ibmlongdouble and -mabi=ieeelongdouble are implemented
to override the configuration defaults.

Bootstrapped on power8 and power9 machines.

gcc/m2/ChangeLog:

	PR modula2/111956
	* Make-lang.in (host_mc_longreal): Remove.
	* configure: Regenerate.
	* configure.ac (M2C_LONGREAL_FLOAT128): Remove.
	(M2C_LONGREAL_PPC64LE): Remove.
	* gm2-compiler/M2Options.def (SetIBMLongDouble): New procedure.
	(GetIBMLongDouble): New procedure function.
	(SetIEEELongDouble): New procedure.
	(GetIEEELongDouble): New procedure function.
	* gm2-compiler/M2Options.mod (SetIBMLongDouble): New procedure.
	(GetIBMLongDouble): New procedure function.
	(SetIEEELongDouble): New procedure.
	(GetIEEELongDouble): New procedure function.
	(InitializeLongDoubleFlags): New procedure called during
	module block initialization.
	* gm2-gcc/m2configure.cc: Remove duplicate includes.
	(m2configure_M2CLongRealFloat128): Remove.
	(m2configure_M2CLongRealIBM128): Remove.
	(m2configure_M2CLongRealLongDouble): Remove.
	(m2configure_M2CLongRealLongDoublePPC64LE): Remove.
	(m2configure_TargetIEEEQuadDefault): New function.
	* gm2-gcc/m2configure.def (M2CLongRealFloat128): Remove.
	(M2CLongRealIBM128): Remove.
	(M2CLongRealLongDouble): Remove.
	(M2CLongRealLongDoublePPC64LE): Remove.
	(TargetIEEEQuadDefault): New function.
	* gm2-gcc/m2configure.h (m2configure_M2CLongRealFloat128): Remove.
	(m2configure_M2CLongRealIBM128): Remove.
	(m2configure_M2CLongRealLongDouble): Remove.
	(m2configure_M2CLongRealLongDoublePPC64LE): Remove.
	(m2configure_TargetIEEEQuadDefault): New function.
	* gm2-gcc/m2options.h (M2Options_SetIBMLongDouble): New prototype.
	(M2Options_GetIBMLongDouble): New prototype.
	(M2Options_SetIEEELongDouble): New prototype.
	(M2Options_GetIEEELongDouble): New prototype.
	* gm2-gcc/m2type.cc (build_m2_long_real_node): Re-implement using
	results of M2Options_GetIBMLongDouble and M2Options_GetIEEELongDouble.
	* gm2-lang.cc (gm2_langhook_handle_option): Add case
	OPT_mabi_ibmlongdouble and call M2Options_SetIBMLongDouble.
	Add case OPT_mabi_ieeelongdouble and call M2Options_SetIEEELongDouble.
	* gm2config.aci.in: Regenerate.
	* gm2spec.cc (lang_specific_driver): Remove block defined by
	M2C_LONGREAL_PPC64LE.
	Remove case OPT_mabi_ibmlongdouble.
	Remove case OPT_mabi_ieeelongdouble.

libgm2/ChangeLog:

	PR modula2/111956
	* Makefile.am (TARGET_LONGDOUBLE_ABI): Remove.
	* Makefile.in: Regenerate.
	* libm2cor/Makefile.am (TARGET_LONGDOUBLE_ABI): Remove.
	* libm2cor/Makefile.in: Regenerate.
	* libm2iso/Makefile.am (TARGET_LONGDOUBLE_ABI): Remove.
	* libm2iso/Makefile.in: Regenerate.
	* libm2log/Makefile.am (TARGET_LONGDOUBLE_ABI): Remove.
	* libm2log/Makefile.in: Regenerate.
	* libm2min/Makefile.am (TARGET_LONGDOUBLE_ABI): Remove.
	* libm2min/Makefile.in: Regenerate.
	* libm2pim/Makefile.am (TARGET_LONGDOUBLE_ABI): Remove.
	* libm2pim/Makefile.in: Regenerate.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-01-18 13:06:30 +00:00
H.J. Lu
af66955000 hwasan: Check if Intel LAM_U57 is enabled
When -fsanitize=hwaddress is used, libhwasan will try to enable LAM_U57
in the startup code.  Update the target check to enable hwaddress tests
if LAM_U57 is enabled.  Also compile hwaddress tests with -mlam=u57 on
x86-64 since hwasan requires LAM_U57 on x86-64.

	* lib/hwasan-dg.exp (check_effective_target_hwaddress_exec):
	Return 1 if Intel LAM_U57 is enabled.
	(hwasan_init): Add -mlam=u57 on x86-64.
2024-01-18 05:03:57 -08:00
Jonathan Wakely
ac913d5d51 libstdc++: Avoid -Wmaybe-uninitialized warnings in text_encoding.cc
These variables are only read from if we haven't reached the end of
either range, in which case they're guaranteed to be initialized to the
next alphanumeric character. But we can just initialize them to make the
compiler happy.

libstdc++-v3/ChangeLog:

	* include/bits/unicode.h (__charset_alias_match): Initialize
	__var_a and __var_b.
2024-01-18 12:43:32 +00:00
Jonathan Wakely
db42a0a989 libstdc++: Fix std::format test for Solaris [PR113450]
When int8_t is a typedef for char (rather than signed char) this test
fails because it tries to format a char, which is treated differently
from formatting other integral types (including signed char).

Use signed char explicitly so the result doesn't depend on the
non-portable definition of int8_t.

libstdc++-v3/ChangeLog:

	PR libstdc++/113450
	* testsuite/std/format/functions/format.cc: Use signed char
	instead of int8_t.
2024-01-18 12:43:31 +00:00
Richard Biener
1c1853a70f Fix memory leak in vect_analyze_loop_form
The following fixes a memory leak in vect_analyze_loop_form which fails
to free the loop body it gets.  It also allows more countable exits,
matching what we can handle later, when we decide which exit to use
as main exit.  Finally some no longer applying comments are adjusted.

	* tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
	prefer all later exits we can handle.
	(vect_analyze_loop_form): Free the allocated loop body.
	Adjust comments.
2024-01-18 13:17:31 +01:00
Georg-Johann Lay
695f615f98 AVR: Tabify avr-log.cc.
gcc/
	* config/avr/avr-log.cc: Tabify.
2024-01-18 12:29:13 +01:00
Juzhe-Zhong
38d8facddf RISC-V: Support vi variant for vec_cmp
While running various benchmarks, I notice we miss vi variant support for integer comparison.
That is, we can vectorize code into vadd.vi but we can't vectorize into vmseq.vi.

Consider this following case:

void
foo (int n, int **__restrict a)
{
  int b;
  int c;
  int d;
  for (b = 0; b < n; b++)
    for (long e = 8; e > 0; e--)
      a[b][e] = a[b][e] == 15;
}

Before this patch:

        vsetivli        zero,4,e32,m1,ta,ma
        vmv.v.i v4,15
        vmv.v.i v3,1
        vmv.v.i v2,0
.L3:
        ld      a5,0(a1)
        addi    a4,a5,4
        addi    a5,a5,20
        vle32.v v1,0(a5)
        vle32.v v0,0(a4)
        vmseq.vv        v0,v0,v4

After this patch:

        ld      a5,0(a1)
        addi    a4,a5,4
        addi    a5,a5,20
        vle32.v v1,0(a5)
        vle32.v v0,0(a4)
        vmseq.vi        v0,v0,15

It's the missing feature caused by our some mistakes, support vi variant for vec_cmp like other patterns (add, sub, ..., etc).

Tested with no regression, ok for trunk ?

gcc/ChangeLog:

	* config/riscv/autovec.md: Support vi variant.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c: New test.
	* gcc.target/riscv/rvv/autovec/cmp/macro.h: New test.
2024-01-18 19:17:02 +08:00
Georg-Johann Lay
95d4363696 AVR: Tabify avr-devices.cc.
gcc/
	* config/avr/avr-devices.cc: Tabify.
2024-01-18 12:10:59 +01:00
Georg-Johann Lay
eef0bffa46 AVR: Tabify avr-c.cc.
gcc/
	* config/avr/avr-c.cc: Tabify.
2024-01-18 12:03:22 +01:00
Georg-Johann Lay
37be539c8a AVR: Tabify driver-avr.cc.
gcc/
	* config/avr/driver-avr.cc: Tabify.
2024-01-18 11:57:09 +01:00
Georg-Johann Lay
1d586c5b06 AVR: Tabify gen-avr-mmcu-texi.cc.
gcc/
	* config/avr/gen-avr-mmcu-texi.cc: Tabify.
2024-01-18 11:57:08 +01:00
Georg-Johann Lay
66128fb875 AVR: Tabify gen-avr-mmcu-specs.cc.
gcc/
	* config/avr/gen-avr-mmcu-specs.cc: Tabify.
2024-01-18 11:57:07 +01:00
Jakub Jelinek
3c7add6af4 riscv: Remove Bool keywords from riscv.opt
As I wrote recently, Bool is an undocumented unsupported keyword, as
can be seen by
grep Bool doc/options.texi *.awk
The option parsing just parses and ignores all keywords it doesn't handle.
But, because it isn't a supported keyword, I think we shouldn't have it in
*.opt files, because that just means people copy it over to other places
even when it doesn't have any effect.

Tested with a cross to riscv64-linux, none of the generated
options.{h,cc} options-{save,urls}.cc
files change with the patch, only optionlist does (but that is just
used as a source for those files).

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

	* config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
	minline-strcmp, minline-strncmp, minline-strlen,
	-param=riscv-vector-abi): Remove Bool keywords.
2024-01-18 10:24:25 +01:00
Jakub Jelinek
d4a2d91b46 i386: Add -masm=intel profiling support [PR113122]
x86_function_profiler emits assembly directly into file and only emits
AT&T syntax.  The following patch adjusts it to emit MASM syntax
if -masm=intel.
As it doesn't use asm_fprintf, I can't use {|} syntax for the dialects.

I've tested using
for i in -mcmodel=large "-mcmodel=large -fpic" "" -fpic "-m32 -fpic" "-m32"; do
./xgcc -B ./ -c -O2 -fprofile $i -masm=att pr113122.c -o pr113122.o1;
./xgcc -B ./ -c -O2 -fprofile $i -masm=intel pr113122.c -o pr113122.o2;
objdump -dr pr113122.o1 > /tmp/1; objdump -dr pr113122.o2 > /tmp/2;
diff -up /tmp/1 /tmp/2; done
that the emitted sequences are identical after assembly.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

	PR target/113122
	* config/i386/i386.cc (x86_function_profiler): Add -masm=intel
	support.  Add missing space after , in emitted assembly in some
	cases.  Formatting fixes.

	* gcc.target/i386/pr113122-1.c: New test.
	* gcc.target/i386/pr113122-2.c: New test.
	* gcc.target/i386/pr113122-3.c: New test.
	* gcc.target/i386/pr113122-4.c: New test.
2024-01-18 10:21:12 +01:00
Xi Ruoyao
b4cb9c9606
LoongArch: Remove constraint z from movsi_internal
We don't allow SImode in FCC, so constraint z is never really used
here.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (movsi_internal): Remove
	constraint z.
2024-01-18 17:07:41 +08:00
Georg-Johann Lay
f8138d7e26 AVR: Fix typo in device-specs generation. Reuse -m[no-]rodata-in-ram checker.
gcc/
	* config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
	in the diagnostic, and capitalize the device name.
	(print_mcu): Generate specs such that:
	<*check_rodata_in_ram>: New.
	<*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
	<*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
	<*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
2024-01-18 10:01:16 +01:00
Arthur Cohen
2341df1cb9 rust_debug: Cast size_t values to unsigned long before printing.
Using %lu to format size_t values breaks 32 bit targets, and %zu is not
supported by one of the hosts GCC aims to support - HPUX

gcc/rust/ChangeLog:

	* backend/rust-compile-base.cc (HIRCompileBase::resolve_method_address):
	Cast size_t value to unsigned long.
	* expand/rust-proc-macro.cc (load_macros): Likewise.
	* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit): Likewise.
2024-01-18 09:54:31 +01:00
Jakub Jelinek
484f48f03c testsuite: Fix up scev-16.c test [PR113446]
This test FAILs on i686-linux or e.g. sparc*-solaris*, because
it uses vect_int effective target outside of */vect/ testsuite.
That is wrong, vect_int assumes the extra added flags by vect.exp
by default, which aren't added in other testsuites.

The following patch fixes that by moving the test into gcc.dg/vect/
and doing small tweaks.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/112774
	PR testsuite/113446
	* gcc.dg/tree-ssa/scev-16.c: Move test ...
	* gcc.dg/vect/pr112774.c: ... here.  Add PR comment line, use
	dg-additional-options instead of dg-options and drop
	-fdump-tree-vect-details.
2024-01-18 08:51:53 +01:00
Jakub Jelinek
b032f4b7da testsuite: Fix up gcc.target/i386/sse4_1-stv-1.c test [PR113452]
From what I can see, this test has been written for a backend fix and
assumes the loop isn't vectorized (at least, it wasn't when the test was
added, it contains an early exit), but that is no longer true and because
of the vectorization it now contains an instruction which the test scans
for not being present.

I think we should just disable vectorization here.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

	PR testsuite/113452
	* gcc.target/i386/sse4_1-stv-1.c: Add -fno-tree-vectorize to
	dg-options.
2024-01-18 08:46:15 +01:00
Jakub Jelinek
1203fc2e6a opts: Fix up -ffold-mem-offsets option keywords
While the option was originally meant to be a Target option for a single
target, it is an option for all targets, so should be Common rather than
Target, and because it is an optimization option which could be different
in between different LTO TUs, I've added Optimization keyword too.
From what I can see, Bool is a non-documented non-existing keyword (at
least, grep Bool *.awk shows nothing, so I've dropped that too.  Seems
that the option parsing simply parses and ignores any non-existing keywords.

Guess we should drop the Bool keywords from the gcc/config/riscv/riscv.opt
file eventually, so that people don't copy this around.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

	PR other/113399
	* common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
	Common and Optimization.
2024-01-18 08:45:09 +01:00