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Revert "RISC-V: Add non-vector types to dfa pipelines"

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This reverts commit 26c34b809c.
This commit is contained in:
Edwin Lu 2024-01-31 21:50:58 -08:00
parent 2a30dd3a76
commit fd4829dde4
6 changed files with 66 additions and 102 deletions
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15
gcc/config/riscv/generic-ooo.md
View file

@ -115,20 +115,9 @@
(define_insn_reservation "generic_ooo_alu" 1
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\
condmove,mvpair,zicond"))
move,bitmanip,min,max,minu,maxu,clz,ctz"))
"generic_ooo_issue,generic_ooo_ixu_alu")
(define_insn_reservation "generic_ooo_sfb_alu" 2
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "sfb_alu"))
"generic_ooo_issue,generic_ooo_ixu_alu")
;; Branch instructions
(define_insn_reservation "generic_ooo_branch" 1
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "branch,jump,call,jalr,ret,trap"))
"generic_ooo_issue,generic_ooo_ixu_alu")
;; Float move, convert and compare.
(define_insn_reservation "generic_ooo_float_move" 3
@ -195,7 +184,7 @@
(define_insn_reservation "generic_ooo_vec_alu" 3
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector float comparison, conversion etc.

20
gcc/config/riscv/generic.md
View file

@ -27,9 +27,7 @@
(define_insn_reservation "generic_alu" 1
(and (eq_attr "tune" "generic")
(eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,\
condmove,crypto,mvpair,zicond"))
(eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
"alu")
(define_insn_reservation "generic_load" 3
@ -49,17 +47,12 @@
(define_insn_reservation "generic_branch" 1
(and (eq_attr "tune" "generic")
(eq_attr "type" "branch,jump,call,jalr,ret,trap"))
"alu")
(define_insn_reservation "generic_sfb_alu" 2
(and (eq_attr "tune" "generic")
(eq_attr "type" "sfb_alu"))
(eq_attr "type" "branch,jump,call,jalr"))
"alu")
(define_insn_reservation "generic_imul" 10
(and (eq_attr "tune" "generic")
(eq_attr "type" "imul,clmul,cpop"))
(eq_attr "type" "imul,clmul"))
"imuldiv*10")
(define_insn_reservation "generic_idivsi" 34
@ -74,12 +67,6 @@
(eq_attr "mode" "DI")))
"imuldiv*66")
(define_insn_reservation "generic_fmul_half" 5
(and (eq_attr "tune" "generic")
(and (eq_attr "type" "fadd,fmul,fmadd")
(eq_attr "mode" "HF")))
"alu")
(define_insn_reservation "generic_fmul_single" 5
(and (eq_attr "tune" "generic")
(and (eq_attr "type" "fadd,fmul,fmadd")
@ -101,4 +88,3 @@
(and (eq_attr "tune" "generic")
(eq_attr "type" "fsqrt"))
"fdivsqrt*25")

18
gcc/config/riscv/riscv.md
View file

@ -326,7 +326,9 @@
;; rotate rotation instructions
;; atomic atomic instructions
;; condmove conditional moves
;; cbo cache block instructions
;; crypto cryptography instructions
;; pushpop zc push and pop instructions
;; mvpair zc move pair instructions
;; zicond zicond instructions
;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
@ -466,8 +468,8 @@
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
atomic,condmove,crypto,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,
vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,
atomic,condmove,cbo,crypto,pushpop,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,
rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
@ -3671,7 +3673,7 @@
UNSPECV_CLEAN)]
"TARGET_ZICBOM"
"cbo.clean\t%a0"
[(set_attr "type" "store")]
[(set_attr "type" "cbo")]
)
(define_insn "riscv_flush_<mode>"
@ -3679,7 +3681,7 @@
UNSPECV_FLUSH)]
"TARGET_ZICBOM"
"cbo.flush\t%a0"
[(set_attr "type" "store")]
[(set_attr "type" "cbo")]
)
(define_insn "riscv_inval_<mode>"
@ -3687,7 +3689,7 @@
UNSPECV_INVAL)]
"TARGET_ZICBOM"
"cbo.inval\t%a0"
[(set_attr "type" "store")]
[(set_attr "type" "cbo")]
)
(define_insn "riscv_zero_<mode>"
@ -3695,7 +3697,7 @@
UNSPECV_ZERO)]
"TARGET_ZICBOZ"
"cbo.zero\t%a0"
[(set_attr "type" "store")]
[(set_attr "type" "cbo")]
)
(define_insn "prefetch"
@ -3711,7 +3713,7 @@
default: gcc_unreachable ();
}
}
[(set_attr "type" "store")])
[(set_attr "type" "cbo")])
(define_insn "riscv_prefetchi_<mode>"
[(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
@ -3719,7 +3721,7 @@
UNSPECV_PREI)]
"TARGET_ZICBOP"
"prefetch.i\t%a0"
[(set_attr "type" "store")])
[(set_attr "type" "cbo")])
(define_expand "extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")

17
gcc/config/riscv/sifive-7.md
View file

@ -34,7 +34,7 @@
(define_insn_reservation "sifive_7_branch" 1
(and (eq_attr "tune" "sifive_7")
(eq_attr "type" "branch,ret,trap"))
(eq_attr "type" "branch"))
"sifive_7_B")
(define_insn_reservation "sifive_7_sfb_alu" 2
@ -59,8 +59,7 @@
(define_insn_reservation "sifive_7_alu" 2
(and (eq_attr "tune" "sifive_7")
(eq_attr "type" "unknown,arith,shift,slt,multi,logical,move,bitmanip,\
rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,crypto,mvpair,zicond"))
(eq_attr "type" "unknown,arith,shift,slt,multi,logical,move"))
"sifive_7_A|sifive_7_B")
(define_insn_reservation "sifive_7_load_immediate" 1
@ -68,12 +67,6 @@
(eq_attr "type" "nop,const,auipc"))
"sifive_7_A|sifive_7_B")
(define_insn_reservation "sifive_7_hfma" 5
(and (eq_attr "tune" "sifive_7")
(and (eq_attr "type" "fadd,fmul,fmadd")
(eq_attr "mode" "HF")))
"sifive_7_B")
(define_insn_reservation "sifive_7_sfma" 5
(and (eq_attr "tune" "sifive_7")
(and (eq_attr "type" "fadd,fmul,fmadd")
@ -113,12 +106,6 @@
(eq_attr "type" "mfc"))
"sifive_7_A")
;; Popcount and clmul.
(define_insn_reservation "sifive_7_popcount" 2
(and (eq_attr "tune" "sifive_7")
(eq_attr "type" "cpop,clmul"))
"sifive_7_A")
(define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
"sifive_7_alu,sifive_7_branch")

2
gcc/config/riscv/vector.md
View file

@ -1054,7 +1054,7 @@
(reg:SI FRM_REGNUM))]
"TARGET_VECTOR"
"frrm\t%0"
[(set_attr "type" "fmove")
[(set_attr "type" "rdfrm")
(set_attr "mode" "SI")]
)

96
gcc/config/riscv/zc.md
View file

@ -27,7 +27,7 @@
(const_int <slot0_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@ -41,7 +41,7 @@
(const_int <slot1_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@ -58,7 +58,7 @@
(const_int <slot2_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s1}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@ -78,7 +78,7 @@
(const_int <slot3_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s2}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@ -101,7 +101,7 @@
(const_int <slot4_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s3}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@ -127,7 +127,7 @@
(const_int <slot5_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s4}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@ -156,7 +156,7 @@
(const_int <slot6_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s5}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@ -188,7 +188,7 @@
(const_int <slot7_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s6}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@ -223,7 +223,7 @@
(const_int <slot8_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s7}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@ -261,7 +261,7 @@
(const_int <slot9_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s8}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@ -302,7 +302,7 @@
(const_int <slot10_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s9}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@ -349,7 +349,7 @@
(const_int <slot12_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s11}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_ra_<mode>"
[(set (reg:X SP_REGNUM)
@ -362,7 +362,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@ -378,7 +378,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@ -397,7 +397,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s1}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@ -419,7 +419,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s2}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@ -444,7 +444,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s3}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@ -472,7 +472,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s4}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@ -503,7 +503,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s5}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@ -537,7 +537,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s6}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@ -574,7 +574,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s7}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@ -614,7 +614,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s8}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@ -657,7 +657,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s9}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@ -706,7 +706,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s11}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
[(set (reg:X SP_REGNUM)
@ -722,7 +722,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@ -741,7 +741,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@ -763,7 +763,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s1}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@ -788,7 +788,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s2}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@ -816,7 +816,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s3}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@ -847,7 +847,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s4}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@ -881,7 +881,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s5}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@ -918,7 +918,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s6}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@ -958,7 +958,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s7}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@ -1001,7 +1001,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s8}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@ -1047,7 +1047,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s9}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@ -1099,7 +1099,7 @@
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s11}, %0"
[(set_attr "type" "load")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_ra_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1110,7 +1110,7 @@
(match_operand 0 "stack_push_up_to_ra_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s0_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1124,7 +1124,7 @@
(match_operand 0 "stack_push_up_to_s0_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s1_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1141,7 +1141,7 @@
(match_operand 0 "stack_push_up_to_s1_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s1}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s2_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1161,7 +1161,7 @@
(match_operand 0 "stack_push_up_to_s2_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s2}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s3_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1184,7 +1184,7 @@
(match_operand 0 "stack_push_up_to_s3_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s3}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s4_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1210,7 +1210,7 @@
(match_operand 0 "stack_push_up_to_s4_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s4}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s5_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1239,7 +1239,7 @@
(match_operand 0 "stack_push_up_to_s5_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s5}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s6_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1271,7 +1271,7 @@
(match_operand 0 "stack_push_up_to_s6_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s6}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s7_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1306,7 +1306,7 @@
(match_operand 0 "stack_push_up_to_s7_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s7}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s8_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1344,7 +1344,7 @@
(match_operand 0 "stack_push_up_to_s8_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s8}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s9_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1385,7 +1385,7 @@
(match_operand 0 "stack_push_up_to_s9_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s9}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s11_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@ -1432,7 +1432,7 @@
(match_operand 0 "stack_push_up_to_s11_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s11}, %0"
[(set_attr "type" "store")])
[(set_attr "type" "pushpop")])
;; ZCMP mv
(define_insn "*mva01s<X:mode>"