Add PowerPC target attribute/pragma support
From-SVN: r166947
This commit is contained in:
Michael Meissner
Michael Meissner
parent
69ccdddbb8
commit
fd438373cd
25 changed files with 2379 additions and 701 deletions
227
gcc/ChangeLog
227
gcc/ChangeLog
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@ -1,3 +1,230 @@
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2010-11-19 Michael Meissner <meissner@linux.vnet.ibm.com>
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* doc/extend.texi (Function attributes): Document PowerPC target
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attributes that are supported.
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(Pragmas): Document that PowerPC now supports target pragmas.
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* doc/options.texi (TargetVariable): Document TargetVariable,
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HeaderInclude, and SourceInclude.
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* doc/invoke.texi (-mfused-madd): Document that -mfused-madd is
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mapped to -ffp-contract=fast, and -mno-fused-madd is mapped to
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-ffp-contract=off.
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* optc-gen.awk: Add support for TargetVariable, HeaderInclude, and
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SourceInclude directives. Fix a cut+paste error with target save
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enum variables. Sort enums in the structures after ints and
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before shorts.
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* opth-gen.awk: Ditto.
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* configure.ac: Add support for HeaderInclude and SourceInclude
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option directives to add the appropriate files to the dependency
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lists.
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* configure: Regenerate.
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* Makefile.in (OPTIONS_H_EXTRA): New variable for HeaderInclude.
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(OPTIONS_C_EXTRA): New variable for SourceInclude.
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(OPTIONS_H): Add $(OPTIONS_H_EXTRA).
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(options.o): Add $(OPTIONS_C_EXTRA) dependency.
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(gcc-options.o): Ditto.
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* opt-include.awk: New awk script to handle HeaderInclude and
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TargetInclude.
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* config/rs6000/aix.opt (-mxl-compat): Mark option as Save so it
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gets saved in the target options.
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* config/rs6000/linux64.opt (-mprofile-kernel): Ditto.
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* config/rs6000/sysv4.opt (-mbit-align): Ditto.
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(-mprototype): Ditto.
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(-mbit-word): ditto.
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(-mregnames): Ditto.
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(-msecure-plt): Ditto.
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(-mbss-plt): Ditto.
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* config/rs6000/rs6000.opt (-mpowerpc-gpopt): Ditto.
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(-mpowerpc-gfxopt): Ditto.
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(-mmfcrf): Ditto.
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(-mpopcntb): Ditto.
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(-mfprnd): Ditto.
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(-mcmpb): Ditto.
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(-mmmfpgpr): Ditto.
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(-maltivec): Ditto.
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(-mhard-dfp): Ditto.
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(-mmulhw): Ditto.
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(-mdlmzb): Ditto.
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(-mmultiple): Ditto.
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(-mstring): Ditto.
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(-mpopcntd): Ditto.
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(-mfriz): Ditto.
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(-mvsx): Ditto.
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(-mno-update): Ditto.
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(-mavoid-indexed-addresses): Ditto.
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(-mtls-markers): Ditto.
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(-msched-epilog): Ditto.
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(-msched-prolog): Ditto.
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(-maix-struct-return): Ditto.
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(-msvr4-struct-return): Ditto.
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(-mxl-compat): Ditto.
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(-mrecip-precision): Ditto.
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(-mfp-in-toc): Ditto.
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(-msum-in-toc): Ditto.
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(-mvrsave): Ditto.
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(-mblock-move-inline-limit=): Ditto.
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(-misel): Ditto.
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(-mpaired): Ditto.
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(-mlongcall): Ditto.
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(-mgen-cell-microcode): Ditto.
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(-mwarn-cell-microcode): Ditto.
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(-mwarn-altivec-long): Ditto.
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(-mprioritize-restricted-insns=): Ditto.
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(-msingle-float): Ditto.
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(-mdouble-float): Ditto.
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(-msimple-fpu): Ditto.
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(-mxilinx-fpu): Ditto.
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* config/rs6000/aix64.opt (-mpe): Ditto.
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* config/rs6000/rs6000.opt (HeaderInclude): Include rs6000-opts.h.
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(rs6000_cpu): Move variable to be a target variable. Rename
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cmodel to rs6000_current_cmodel because of macro conflict. Merge
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-mdebug=<xxx> variables into a single int.
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(rs6000_always_hint): Ditto.
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(rs6000_sched_groups): Ditto.
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(rs6000_align_branch_targets): Ditto.
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(rs6000_sched_costly_dep): Ditto.
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(rs6000_sched_insert_nops): Ditto.
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(rs6000_long_double_type_size): Ditto.
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(rs6000_ieeequad): Ditto.
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(rs6000_altivec_abi): Ditto.
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(rs6000_spe): Ditto.
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(rs6000_spe_abi): Ditto.
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(rs6000_float_gprs): Ditto.
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(rs6000_darwin64_abi): Ditto.
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(can_override_loop_align): Ditto.
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(rs6000_sdata): Ditto.
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(rs6000_tls_size): Ditto.
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(rs6000_current_abi): Ditto.
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(rs6000_traceback): Ditto.
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(rs6000_alignment_flags): Ditto.
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(rs6000_current_cmodel): Ditto.
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(rs6000_recip_control): Ditto.
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(rs6000_cpu_index): Ditto.
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(rs6000_tune_index): Ditto.
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(rs6000_debug): Ditto.
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(rs6000_target_flags_explict): Ditto.
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* config/rs6000/rs6000-protos.h (rs6000_pragma_target_parse): Add
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declaration.
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* config/rs6000/linux64.h (rs6000_current_cmode): Rename from
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cmodel. Change all uses.
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* config/rs6000/rs6000.c (rs6000_always_hint): Move to
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rs6000.opt. Combine -mdebug=<xxx> variables into a single int.
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Rename cmodel to rs6000_current_cmodel.
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(rs6000_sched_groups): Ditto.
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(rs6000_align_branch_targets): Ditto.
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(rs6000_sched_costly_dep): Ditto.
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(rs6000_sched_insert_nops): Ditto.
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(rs6000_long_double_type_size): Ditto.
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(rs6000_ieeequad): Ditto.
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(rs6000_altivec_abi): Ditto.
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(rs6000_spe): Ditto.
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(rs6000_spe_abi): Ditto.
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(rs6000_float_gprs): Ditto.
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(rs6000_darwin64_abi): Ditto.
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(can_override_loop_align): Ditto.
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(rs6000_sdata): Ditto.
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(rs6000_tls_size): Ditto.
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(rs6000_current_abi): Ditto.
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(rs6000_traceback): Ditto.
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(rs6000_alignment_flags): Ditto.
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(rs6000_current_cmodel): Ditto.
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(rs6000_recip_control): Ditto.
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(rs6000_cpu_index): Ditto.
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(rs6000_tune_index): Ditto.
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(rs6000_debug): Ditto.
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(rs6000_target_flags_explict): Ditto.
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(rs6000_sched_insert_nops_str): Make static.
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(rs6000_sched_costly_dep_str): Ditto.
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(rs6000_recip_name): Ditto.
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(rs6000_abi_name): Ditto.
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(rs6000_sdata_name): Ditto.
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(enum rs6000_traceback_name): Move to rs6000-opts.h.
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(rs6000_parse_tls_size_option): Delete.
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(rs6000_valid_attribute_p): New function for target attributes and
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pragmas.
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(rs6000_function_specific_save): Ditto.
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(rs6000_function_specific_restore): Ditto.
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(rs6000_function_specific_print): Ditto.
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(rs6000_can_inline_p): Ditto.
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(rs6000_set_current_function): Ditto.
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(rs6000_inner_target_options): Ditto.
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(rs6000_debug_target_options): Ditto.
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(rs6000_pragma_target_parse): Ditto.
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(TARGET_OPTION_VALID_ATTRIBUTE_P): Define target hooks for target
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attributes and pragmas.
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(TARGET_OPTION_SAVE): Ditto.
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(TARGET_OPTION_RESTORE): Ditto.
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(TARGET_OPTION_PRINT): Ditto.
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(TARGET_CAN_INLINE_P): Ditto.
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(TARGET_SET_CURRENT_FUNCTION): Ditto.
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(POWER_MASKS): Move to file level scope from the
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rs6000_option_override_internal function.
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(POWERPC_MASKS): Ditto.
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(ISA_*_MASKS): Ditto.
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(struct rs6000_ptt): Ditto.
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(processor_target_table): Ditto.
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(rs6000_cpu_name_lookup): Map cpu name to an index in
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processor_target_table.
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(rs6000_debug_reg_global): Print more information on processor
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options for -mdebug=reg.
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(rs6000_init_hard_regno_mode_ok): Add support for target
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attributes and pragmas. Merge all -mdebug=<xxx> fields into one.
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Allow -mdebug=val1,val2. Rename cmodel variable.
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(rs6000_option_override_internal): Ditto.
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(rs6000_option_override): Ditto.
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(rs6000_handle_option): Ditto.
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(rs6000_conditional_register_usage): Add debug trace message.
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(struct rs6000_opt_mask): New for target attribute/pragma
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support.
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(rs6000_opt_masks): Ditto.
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(struct rs6000_opt_var): Ditto.
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(rs6000_opt_vars): Ditto.
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(rs6000_previous_function): Ditto.
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* config/rs6000/rs6000.h (top level): Include rs6000-opts.h if it
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wasn't already included.
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(enum rs6000_cmodel): Move to rs6000-opts.h or rs6000.opt.
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(enum processor_type): Ditto.
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(rs6000_cpu): Ditto.
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(enum fpu_type_t): Ditto.
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(fpu_type): Ditto.
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(enum rs6000_dependence_cost): Ditto.
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(enum rs6000_nop_insertion): Ditto.
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(enum group_termination): Ditto.
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(rs6000_long_double_type_size): Ditto.
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(rs6000_ieeequad): Ditto.
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(rs6000_altivec_abi): Ditto.
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(rs6000_spe_abi): Ditto.
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(rs6000_spe): Ditto.
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(rs6000_float_gprs): Ditto.
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(rs6000_alignment_flags): Ditto.
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(rs6000_sched_insert_nops): Ditto.
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(enum rs6000_vector): Ditto.
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(enum rs6000_abi): Ditto.
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(rs6000_current_opt): Ditto.
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(rs6000_debug_*): Delete.
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(MASK_DEBUG*): Combine -mdebug=xxxx into one int.
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(TARGET_DEBUG*): Ditto.
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* config/rs6000/rs6000-opts.h: New header file to define the enums
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that are used in target variables that are now defined in
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rs6000.opt.
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* config/rs6000/sysv4.h (enum rs6000_sdata_type): Move to
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rs6000-opts.h.
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(rs6000_sdata): Ditto.
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(rs6000_abi_name): Delete.
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(rs6000_sdata_name): Ditto.
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(rs6000_tls_size_string): Ditto.
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2010-11-19 Joseph Myers <joseph@codesourcery.com>
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* common.opt (debug_struct_ordinary, debug_struct_generic): New
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@ -806,6 +806,16 @@ T_TARGET : $(T_TARGET)
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# at build time.
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SPECS = specs
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# Extra include files that are defined by HeaderInclude directives in
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# the .opt files
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OPTIONS_H_EXTRA =
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# Extra include files that are defined by SourceInclude directives in
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# the .opt files
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OPTIONS_C_EXTRA =
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@option_includes@
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# End of variables for you to override.
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# GTM_H lists the config files that the generator files depend on,
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@ -893,7 +903,7 @@ RECOG_H = recog.h
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ALIAS_H = alias.h coretypes.h
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EMIT_RTL_H = emit-rtl.h
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FLAGS_H = flags.h coretypes.h flag-types.h $(OPTIONS_H)
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OPTIONS_H = options.h flag-types.h
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OPTIONS_H = options.h flag-types.h $(OPTIONS_H_EXTRA)
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FUNCTION_H = function.h $(TREE_H) $(HASHTAB_H) vecprim.h $(TM_H)
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EXPR_H = expr.h insn-config.h $(FUNCTION_H) $(RTL_H) $(FLAGS_H) $(TREE_H) $(MACHMODE_H) $(EMIT_RTL_H)
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OPTABS_H = optabs.h insn-codes.h
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@ -2234,9 +2244,10 @@ s-options-h: optionlist $(srcdir)/opt-functions.awk $(srcdir)/opth-gen.awk
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$(STAMP) $@
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options.o: options.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TARGET_H) $(FLAGS_H) \
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$(TM_H) $(OPTS_H) intl.h
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$(TM_H) $(OPTS_H) intl.h $(OPTIONS_C_EXTRA)
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gcc-options.o: options.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(OPTS_H) intl.h
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gcc-options.o: options.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(OPTS_H) intl.h \
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$(OPTIONS_C_EXTRA)
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$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(OUTPUT_OPTION) \
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-DGCC_DRIVER options.c
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@ -20,5 +20,5 @@
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; <http://www.gnu.org/licenses/>.
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mxl-compat
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Target Var(has_xl_compat_option)
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Target Var(has_xl_compat_option) Save
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Conform more closely to IBM XLC semantics
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@ -28,5 +28,5 @@ Target Report RejectNegative Negative(maix64) InverseMask(64BIT)
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Compile for 32-bit pointers
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mpe
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Target Report RejectNegative Var(internal_nothing_1)
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Target Report RejectNegative Var(internal_nothing_1) Save
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Support message passing with the Parallel Environment
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@ -65,10 +65,9 @@ extern int dot_symbols;
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#define TARGET_USES_LINUX64_OPT 1
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#ifdef HAVE_LD_LARGE_TOC
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extern enum rs6000_cmodel cmodel;
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#undef TARGET_CMODEL
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#define TARGET_CMODEL cmodel
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#define SET_CMODEL(opt) cmodel = opt
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#define TARGET_CMODEL rs6000_current_cmodel
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#define SET_CMODEL(opt) rs6000_current_cmodel = opt
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#else
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#define SET_CMODEL(opt) do {} while (0)
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#endif
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@ -127,7 +126,7 @@ extern enum rs6000_cmodel cmodel;
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if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \
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{ \
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if (rs6000_explicit_options.cmodel \
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&& cmodel != CMODEL_SMALL) \
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&& rs6000_current_cmodel != CMODEL_SMALL) \
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error ("-mcmodel incompatible with other toc options"); \
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SET_CMODEL (CMODEL_SMALL); \
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} \
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@ -135,7 +134,7 @@ extern enum rs6000_cmodel cmodel;
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{ \
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if (!rs6000_explicit_options.cmodel) \
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SET_CMODEL (CMODEL_MEDIUM); \
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if (cmodel != CMODEL_SMALL) \
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if (rs6000_current_cmodel != CMODEL_SMALL) \
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{ \
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TARGET_NO_FP_IN_TOC = 0; \
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TARGET_NO_SUM_IN_TOC = 0; \
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@ -20,7 +20,7 @@
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; <http://www.gnu.org/licenses/>.
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mprofile-kernel
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Target Report Var(profile_kernel)
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Target Report Var(profile_kernel) Save
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Call mcount for profiling before a function prologue
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mcmodel=
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144
gcc/config/rs6000/rs6000-opts.h
Normal file
144
gcc/config/rs6000/rs6000-opts.h
Normal file
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@ -0,0 +1,144 @@
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/* Definitions of target machine needed for option handling for GNU compiler,
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for IBM RS/6000.
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Copyright (C) 2010
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Free Software Foundation, Inc.
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Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)
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This file is part of GCC.
|
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GCC is free software; you can redistribute it and/or modify it
|
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under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
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|
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GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
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||||
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||||
#ifndef RS6000_OPTS_H
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#define RS6000_OPTS_H
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/* Processor type. Order must match cpu attribute in MD file. */
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enum processor_type
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{
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PROCESSOR_RIOS1,
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PROCESSOR_RIOS2,
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PROCESSOR_RS64A,
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PROCESSOR_MPCCORE,
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PROCESSOR_PPC403,
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PROCESSOR_PPC405,
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PROCESSOR_PPC440,
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PROCESSOR_PPC476,
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PROCESSOR_PPC601,
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PROCESSOR_PPC603,
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PROCESSOR_PPC604,
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PROCESSOR_PPC604e,
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PROCESSOR_PPC620,
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PROCESSOR_PPC630,
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PROCESSOR_PPC750,
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PROCESSOR_PPC7400,
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PROCESSOR_PPC7450,
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PROCESSOR_PPC8540,
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PROCESSOR_PPCE300C2,
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PROCESSOR_PPCE300C3,
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PROCESSOR_PPCE500MC,
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PROCESSOR_PPCE500MC64,
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PROCESSOR_POWER4,
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PROCESSOR_POWER5,
|
||||
PROCESSOR_POWER6,
|
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PROCESSOR_POWER7,
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PROCESSOR_CELL,
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PROCESSOR_PPCA2,
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PROCESSOR_TITAN
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};
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/* FP processor type. */
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enum fpu_type_t
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{
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FPU_NONE, /* No FPU */
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FPU_SF_LITE, /* Limited Single Precision FPU */
|
||||
FPU_DF_LITE, /* Limited Double Precision FPU */
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FPU_SF_FULL, /* Full Single Precision FPU */
|
||||
FPU_DF_FULL /* Full Double Single Precision FPU */
|
||||
};
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||||
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||||
/* Types of costly dependences. */
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enum rs6000_dependence_cost
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{
|
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max_dep_latency = 1000,
|
||||
no_dep_costly,
|
||||
all_deps_costly,
|
||||
true_store_to_load_dep_costly,
|
||||
store_to_load_dep_costly
|
||||
};
|
||||
|
||||
/* Types of nop insertion schemes in sched target hook sched_finish. */
|
||||
enum rs6000_nop_insertion
|
||||
{
|
||||
sched_finish_regroup_exact = 1000,
|
||||
sched_finish_pad_groups,
|
||||
sched_finish_none
|
||||
};
|
||||
|
||||
/* Dispatch group termination caused by an insn. */
|
||||
enum group_termination
|
||||
{
|
||||
current_group,
|
||||
previous_group
|
||||
};
|
||||
|
||||
/* Enumeration to give which calling sequence to use. */
|
||||
enum rs6000_abi {
|
||||
ABI_NONE,
|
||||
ABI_AIX, /* IBM's AIX */
|
||||
ABI_V4, /* System V.4/eabi */
|
||||
ABI_DARWIN /* Apple's Darwin (OS X kernel) */
|
||||
};
|
||||
|
||||
/* Small data support types. */
|
||||
enum rs6000_sdata_type {
|
||||
SDATA_NONE, /* No small data support. */
|
||||
SDATA_DATA, /* Just put data in .sbss/.sdata, don't use relocs. */
|
||||
SDATA_SYSV, /* Use r13 to point to .sdata/.sbss. */
|
||||
SDATA_EABI /* Use r13 like above, r2 points to .sdata2/.sbss2. */
|
||||
};
|
||||
|
||||
/* Type of traceback to use. */
|
||||
enum rs6000_traceback_type {
|
||||
traceback_default = 0,
|
||||
traceback_none,
|
||||
traceback_part,
|
||||
traceback_full
|
||||
};
|
||||
|
||||
/* Code model for 64-bit linux.
|
||||
small: 16-bit toc offsets.
|
||||
medium: 32-bit toc offsets, static data and code within 2G of TOC pointer.
|
||||
large: 32-bit toc offsets, no limit on static data and code. */
|
||||
enum rs6000_cmodel {
|
||||
CMODEL_SMALL,
|
||||
CMODEL_MEDIUM,
|
||||
CMODEL_LARGE
|
||||
};
|
||||
|
||||
/* Describe which vector unit to use for a given machine mode. */
|
||||
enum rs6000_vector {
|
||||
VECTOR_NONE, /* Type is not a vector or not supported */
|
||||
VECTOR_ALTIVEC, /* Use altivec for vector processing */
|
||||
VECTOR_VSX, /* Use VSX for vector processing */
|
||||
VECTOR_PAIRED, /* Use paired floating point for vectors */
|
||||
VECTOR_SPE, /* Use SPE for vector processing */
|
||||
VECTOR_OTHER /* Some other vector unit */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -175,6 +175,9 @@ extern void rs6000_aix_asm_output_dwarf_table_ref (char *);
|
|||
|
||||
extern void rs6000_pragma_longcall (struct cpp_reader *);
|
||||
extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
|
||||
#ifdef TREE_CODE
|
||||
extern bool rs6000_pragma_target_parse (tree, tree);
|
||||
#endif
|
||||
|
||||
#if TARGET_MACHO
|
||||
char *output_call (rtx, rtx *, int, int);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -29,6 +29,10 @@
|
|||
/* Note that some other tm.h files include this one and then override
|
||||
many of the definitions. */
|
||||
|
||||
#ifndef RS6000_OPTS_H
|
||||
#include "config/rs6000/rs6000-opts.h"
|
||||
#endif
|
||||
|
||||
/* Definitions for the object file format. These are set at
|
||||
compile-time. */
|
||||
|
||||
|
|
@ -299,16 +303,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|
|||
#define TARGET_SECURE_PLT 0
|
||||
#endif
|
||||
|
||||
/* Code model for 64-bit linux.
|
||||
small: 16-bit toc offsets.
|
||||
medium: 32-bit toc offsets, static data and code within 2G of TOC pointer.
|
||||
large: 32-bit toc offsets, no limit on static data and code. */
|
||||
enum rs6000_cmodel {
|
||||
CMODEL_SMALL,
|
||||
CMODEL_MEDIUM,
|
||||
CMODEL_LARGE
|
||||
};
|
||||
|
||||
#ifndef TARGET_CMODEL
|
||||
#define TARGET_CMODEL CMODEL_SMALL
|
||||
#endif
|
||||
|
|
@ -338,40 +332,6 @@ enum rs6000_cmodel {
|
|||
|
||||
#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
|
||||
|
||||
/* Processor type. Order must match cpu attribute in MD file. */
|
||||
enum processor_type
|
||||
{
|
||||
PROCESSOR_RIOS1,
|
||||
PROCESSOR_RIOS2,
|
||||
PROCESSOR_RS64A,
|
||||
PROCESSOR_MPCCORE,
|
||||
PROCESSOR_PPC403,
|
||||
PROCESSOR_PPC405,
|
||||
PROCESSOR_PPC440,
|
||||
PROCESSOR_PPC476,
|
||||
PROCESSOR_PPC601,
|
||||
PROCESSOR_PPC603,
|
||||
PROCESSOR_PPC604,
|
||||
PROCESSOR_PPC604e,
|
||||
PROCESSOR_PPC620,
|
||||
PROCESSOR_PPC630,
|
||||
PROCESSOR_PPC750,
|
||||
PROCESSOR_PPC7400,
|
||||
PROCESSOR_PPC7450,
|
||||
PROCESSOR_PPC8540,
|
||||
PROCESSOR_PPCE300C2,
|
||||
PROCESSOR_PPCE300C3,
|
||||
PROCESSOR_PPCE500MC,
|
||||
PROCESSOR_PPCE500MC64,
|
||||
PROCESSOR_POWER4,
|
||||
PROCESSOR_POWER5,
|
||||
PROCESSOR_POWER6,
|
||||
PROCESSOR_POWER7,
|
||||
PROCESSOR_CELL,
|
||||
PROCESSOR_PPCA2,
|
||||
PROCESSOR_TITAN
|
||||
};
|
||||
|
||||
/* FPU operations supported.
|
||||
Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
|
||||
also test TARGET_HARD_FLOAT. */
|
||||
|
|
@ -381,8 +341,6 @@ enum processor_type
|
|||
#define TARGET_SIMPLE_FPU 0
|
||||
#define TARGET_XILINX_FPU 0
|
||||
|
||||
extern enum processor_type rs6000_cpu;
|
||||
|
||||
/* Recast the processor type to the cpu attribute. */
|
||||
#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
|
||||
|
||||
|
|
@ -396,47 +354,12 @@ extern enum processor_type rs6000_cpu;
|
|||
#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
|
||||
#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
|
||||
|
||||
/* FP processor type. */
|
||||
enum fpu_type_t
|
||||
{
|
||||
FPU_NONE, /* No FPU */
|
||||
FPU_SF_LITE, /* Limited Single Precision FPU */
|
||||
FPU_DF_LITE, /* Limited Double Precision FPU */
|
||||
FPU_SF_FULL, /* Full Single Precision FPU */
|
||||
FPU_DF_FULL /* Full Double Single Precision FPU */
|
||||
};
|
||||
|
||||
extern enum fpu_type_t fpu_type;
|
||||
|
||||
/* Specify the dialect of assembler to use. New mnemonics is dialect one
|
||||
and the old mnemonics are dialect zero. */
|
||||
#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
|
||||
|
||||
/* Types of costly dependences. */
|
||||
enum rs6000_dependence_cost
|
||||
{
|
||||
max_dep_latency = 1000,
|
||||
no_dep_costly,
|
||||
all_deps_costly,
|
||||
true_store_to_load_dep_costly,
|
||||
store_to_load_dep_costly
|
||||
};
|
||||
|
||||
/* Types of nop insertion schemes in sched target hook sched_finish. */
|
||||
enum rs6000_nop_insertion
|
||||
{
|
||||
sched_finish_regroup_exact = 1000,
|
||||
sched_finish_pad_groups,
|
||||
sched_finish_none
|
||||
};
|
||||
|
||||
/* Dispatch group termination caused by an insn. */
|
||||
enum group_termination
|
||||
{
|
||||
current_group,
|
||||
previous_group
|
||||
};
|
||||
|
||||
/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
|
||||
struct rs6000_cpu_select
|
||||
{
|
||||
|
|
@ -449,42 +372,25 @@ struct rs6000_cpu_select
|
|||
extern struct rs6000_cpu_select rs6000_select[];
|
||||
|
||||
/* Debug support */
|
||||
extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
|
||||
extern int rs6000_debug_stack; /* debug stack applications */
|
||||
extern int rs6000_debug_arg; /* debug argument handling */
|
||||
extern int rs6000_debug_reg; /* debug register handling */
|
||||
extern int rs6000_debug_addr; /* debug memory addressing */
|
||||
extern int rs6000_debug_cost; /* debug rtx_costs */
|
||||
#define MASK_DEBUG_STACK 0x01 /* debug stack applications */
|
||||
#define MASK_DEBUG_ARG 0x02 /* debug argument handling */
|
||||
#define MASK_DEBUG_REG 0x04 /* debug register handling */
|
||||
#define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
|
||||
#define MASK_DEBUG_COST 0x10 /* debug rtx codes */
|
||||
#define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
|
||||
#define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
|
||||
| MASK_DEBUG_ARG \
|
||||
| MASK_DEBUG_REG \
|
||||
| MASK_DEBUG_ADDR \
|
||||
| MASK_DEBUG_COST \
|
||||
| MASK_DEBUG_TARGET)
|
||||
|
||||
#define TARGET_DEBUG_STACK rs6000_debug_stack
|
||||
#define TARGET_DEBUG_ARG rs6000_debug_arg
|
||||
#define TARGET_DEBUG_REG rs6000_debug_reg
|
||||
#define TARGET_DEBUG_ADDR rs6000_debug_addr
|
||||
#define TARGET_DEBUG_COST rs6000_debug_cost
|
||||
|
||||
extern const char *rs6000_traceback_name; /* Type of traceback table. */
|
||||
|
||||
/* These are separate from target_flags because we've run out of bits
|
||||
there. */
|
||||
extern int rs6000_long_double_type_size;
|
||||
extern int rs6000_ieeequad;
|
||||
extern int rs6000_altivec_abi;
|
||||
extern int rs6000_spe_abi;
|
||||
extern int rs6000_spe;
|
||||
extern int rs6000_float_gprs;
|
||||
extern int rs6000_alignment_flags;
|
||||
extern const char *rs6000_sched_insert_nops_str;
|
||||
extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
|
||||
|
||||
/* Describe which vector unit to use for a given machine mode. */
|
||||
enum rs6000_vector {
|
||||
VECTOR_NONE, /* Type is not a vector or not supported */
|
||||
VECTOR_ALTIVEC, /* Use altivec for vector processing */
|
||||
VECTOR_VSX, /* Use VSX for vector processing */
|
||||
VECTOR_PAIRED, /* Use paired floating point for vectors */
|
||||
VECTOR_SPE, /* Use SPE for vector processing */
|
||||
VECTOR_OTHER /* Some other vector unit */
|
||||
};
|
||||
#define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
|
||||
#define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
|
||||
#define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
|
||||
#define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
|
||||
#define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
|
||||
#define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
|
||||
|
||||
extern enum rs6000_vector rs6000_vector_unit[];
|
||||
|
||||
|
|
@ -628,6 +534,7 @@ extern unsigned char rs6000_recip_bits[];
|
|||
/* Target pragma. */
|
||||
#define REGISTER_TARGET_PRAGMAS() do { \
|
||||
c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
|
||||
targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
|
||||
targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
|
||||
} while (0)
|
||||
|
||||
|
|
@ -1465,16 +1372,6 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
|
|||
|
||||
/* Stack layout; function entry, exit and calling. */
|
||||
|
||||
/* Enumeration to give which calling sequence to use. */
|
||||
enum rs6000_abi {
|
||||
ABI_NONE,
|
||||
ABI_AIX, /* IBM's AIX */
|
||||
ABI_V4, /* System V.4/eabi */
|
||||
ABI_DARWIN /* Apple's Darwin (OS X kernel) */
|
||||
};
|
||||
|
||||
extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
|
||||
|
||||
/* Define this if pushing a word on the stack
|
||||
makes the stack pointer a smaller address. */
|
||||
#define STACK_GROWS_DOWNWARD
|
||||
|
|
|
|||
|
|
@ -20,6 +20,109 @@
|
|||
; along with GCC; see the file COPYING3. If not see
|
||||
; <http://www.gnu.org/licenses/>.
|
||||
|
||||
HeaderInclude
|
||||
config/rs6000/rs6000-opts.h
|
||||
|
||||
;; Current processor
|
||||
TargetVariable
|
||||
enum processor_type rs6000_cpu = PROCESSOR_RIOS1
|
||||
|
||||
;; Always emit branch hint bits.
|
||||
TargetVariable
|
||||
unsigned char rs6000_always_hint
|
||||
|
||||
;; Schedule instructions for group formation.
|
||||
TargetVariable
|
||||
unsigned char rs6000_sched_groups
|
||||
|
||||
;; Align branch targets.
|
||||
TargetVariable
|
||||
unsigned char rs6000_align_branch_targets
|
||||
|
||||
;; Support for -msched-costly-dep option.
|
||||
TargetVariable
|
||||
enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
|
||||
|
||||
;; Support for -minsert-sched-nops option.
|
||||
TargetVariable
|
||||
enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
|
||||
|
||||
;; Size of long double.
|
||||
TargetVariable
|
||||
unsigned char rs6000_long_double_type_size
|
||||
|
||||
;; IEEE quad extended precision long double.
|
||||
TargetVariable
|
||||
unsigned char rs6000_ieeequad
|
||||
|
||||
;; Nonzero to use AltiVec ABI.
|
||||
TargetVariable
|
||||
unsigned char rs6000_altivec_abi
|
||||
|
||||
;; Nonzero if we want SPE SIMD instructions.
|
||||
TargetVariable
|
||||
int rs6000_spe
|
||||
|
||||
;; Nonzero if we want SPE ABI extensions.
|
||||
TargetVariable
|
||||
unsigned char rs6000_spe_abi
|
||||
|
||||
;; Nonzero if floating point operations are done in the GPRs.
|
||||
TargetVariable
|
||||
unsigned char rs6000_float_gprs
|
||||
|
||||
;; Nonzero if we want Darwin's struct-by-value-in-regs ABI.
|
||||
TargetVariable
|
||||
unsigned char rs6000_darwin64_abi
|
||||
|
||||
;; Non-zero to allow overriding loop alignment.
|
||||
TargetVariable
|
||||
unsigned char can_override_loop_align
|
||||
|
||||
;; Which small data model to use (for System V targets only)
|
||||
TargetVariable
|
||||
enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
|
||||
|
||||
;; Bit size of immediate TLS offsets and string from which it is decoded.
|
||||
TargetVariable
|
||||
int rs6000_tls_size = 32
|
||||
|
||||
;; ABI enumeration available for subtarget to use.
|
||||
TargetVariable
|
||||
enum rs6000_abi rs6000_current_abi = ABI_NONE
|
||||
|
||||
;; Type of traceback to use.
|
||||
TargetVariable
|
||||
enum rs6000_traceback_type rs6000_traceback = traceback_default
|
||||
|
||||
;; Control alignment for fields within structures.
|
||||
TargetVariable
|
||||
unsigned char rs6000_alignment_flags
|
||||
|
||||
;; Code model for 64-bit linux.
|
||||
TargetVariable
|
||||
enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
|
||||
|
||||
;; What type of reciprocal estimation instructions to generate
|
||||
TargetVariable
|
||||
unsigned int rs6000_recip_control
|
||||
|
||||
;; -mcpu=<xxx> as an index into the processor_target_table or -1
|
||||
TargetVariable
|
||||
int rs6000_cpu_index = -1
|
||||
|
||||
;; -mtune=<xxx> as an index into the processor_target_table or -1
|
||||
TargetVariable
|
||||
int rs6000_tune_index = -1
|
||||
|
||||
;; Debug flags
|
||||
TargetVariable
|
||||
unsigned int rs6000_debug
|
||||
|
||||
;; Save for target_flags_explicit
|
||||
TargetSave
|
||||
int rs6000_target_flags_explicit
|
||||
|
||||
mpower
|
||||
Target Report RejectNegative Mask(POWER)
|
||||
Use POWER instruction set
|
||||
|
|
@ -45,55 +148,55 @@ Target Report Mask(POWERPC64)
|
|||
Use PowerPC-64 instruction set
|
||||
|
||||
mpowerpc-gpopt
|
||||
Target Report Mask(PPC_GPOPT)
|
||||
Target Report Mask(PPC_GPOPT) Save
|
||||
Use PowerPC General Purpose group optional instructions
|
||||
|
||||
mpowerpc-gfxopt
|
||||
Target Report Mask(PPC_GFXOPT)
|
||||
Target Report Mask(PPC_GFXOPT) Save
|
||||
Use PowerPC Graphics group optional instructions
|
||||
|
||||
mmfcrf
|
||||
Target Report Mask(MFCRF)
|
||||
Target Report Mask(MFCRF) Save
|
||||
Use PowerPC V2.01 single field mfcr instruction
|
||||
|
||||
mpopcntb
|
||||
Target Report Mask(POPCNTB)
|
||||
Target Report Mask(POPCNTB) Save
|
||||
Use PowerPC V2.02 popcntb instruction
|
||||
|
||||
mfprnd
|
||||
Target Report Mask(FPRND)
|
||||
Target Report Mask(FPRND) Save
|
||||
Use PowerPC V2.02 floating point rounding instructions
|
||||
|
||||
mcmpb
|
||||
Target Report Mask(CMPB)
|
||||
Target Report Mask(CMPB) Save
|
||||
Use PowerPC V2.05 compare bytes instruction
|
||||
|
||||
mmfpgpr
|
||||
Target Report Mask(MFPGPR)
|
||||
Target Report Mask(MFPGPR) Save
|
||||
Use extended PowerPC V2.05 move floating point to/from GPR instructions
|
||||
|
||||
maltivec
|
||||
Target Report Mask(ALTIVEC)
|
||||
Target Report Mask(ALTIVEC) Save
|
||||
Use AltiVec instructions
|
||||
|
||||
mhard-dfp
|
||||
Target Report Mask(DFP)
|
||||
Target Report Mask(DFP) Save
|
||||
Use decimal floating point instructions
|
||||
|
||||
mmulhw
|
||||
Target Report Mask(MULHW)
|
||||
Target Report Mask(MULHW) Save
|
||||
Use 4xx half-word multiply instructions
|
||||
|
||||
mdlmzb
|
||||
Target Report Mask(DLMZB)
|
||||
Target Report Mask(DLMZB) Save
|
||||
Use 4xx string-search dlmzb instruction
|
||||
|
||||
mmultiple
|
||||
Target Report Mask(MULTIPLE)
|
||||
Target Report Mask(MULTIPLE) Save
|
||||
Generate load/store multiple instructions
|
||||
|
||||
mstring
|
||||
Target Report Mask(STRING)
|
||||
Target Report Mask(STRING) Save
|
||||
Generate string instructions for block moves
|
||||
|
||||
mnew-mnemonics
|
||||
|
|
@ -113,11 +216,11 @@ Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
|
|||
Use hardware floating point
|
||||
|
||||
mpopcntd
|
||||
Target Report Mask(POPCNTD)
|
||||
Target Report Mask(POPCNTD) Save
|
||||
Use PowerPC V2.06 popcntd instruction
|
||||
|
||||
mfriz
|
||||
Target Report Var(TARGET_FRIZ) Init(-1)
|
||||
Target Report Var(TARGET_FRIZ) Init(-1) Save
|
||||
Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions
|
||||
|
||||
mveclibabi=
|
||||
|
|
@ -125,7 +228,7 @@ Target RejectNegative Joined Var(rs6000_veclibabi_name)
|
|||
Vector library ABI to use
|
||||
|
||||
mvsx
|
||||
Target Report Mask(VSX)
|
||||
Target Report Mask(VSX) Save
|
||||
Use vector/scalar (VSX) instructions
|
||||
|
||||
mvsx-scalar-double
|
||||
|
|
@ -165,7 +268,7 @@ Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1)
|
|||
; Explicitly control whether we vectorize the builtins or not.
|
||||
|
||||
mno-update
|
||||
Target Report RejectNegative Mask(NO_UPDATE)
|
||||
Target Report RejectNegative Mask(NO_UPDATE) Save
|
||||
Do not generate load/store with update instructions
|
||||
|
||||
mupdate
|
||||
|
|
@ -173,30 +276,30 @@ Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE)
|
|||
Generate load/store with update instructions
|
||||
|
||||
mavoid-indexed-addresses
|
||||
Target Report Var(TARGET_AVOID_XFORM) Init(-1)
|
||||
Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
|
||||
Avoid generation of indexed load/store instructions when possible
|
||||
|
||||
mtls-markers
|
||||
Target Report Var(tls_markers) Init(1)
|
||||
Target Report Var(tls_markers) Init(1) Save
|
||||
Mark __tls_get_addr calls with argument info
|
||||
|
||||
msched-epilog
|
||||
Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1)
|
||||
Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
|
||||
|
||||
msched-prolog
|
||||
Target Report Var(TARGET_SCHED_PROLOG)
|
||||
Target Report Var(TARGET_SCHED_PROLOG) Save
|
||||
Schedule the start and end of the procedure
|
||||
|
||||
maix-struct-return
|
||||
Target Report RejectNegative Var(aix_struct_return)
|
||||
Target Report RejectNegative Var(aix_struct_return) Save
|
||||
Return all structures in memory (AIX default)
|
||||
|
||||
msvr4-struct-return
|
||||
Target Report RejectNegative Var(aix_struct_return,0)
|
||||
Target Report RejectNegative Var(aix_struct_return,0) Save
|
||||
Return small structures in registers (SVR4 default)
|
||||
|
||||
mxl-compat
|
||||
Target Report Var(TARGET_XL_COMPAT)
|
||||
Target Report Var(TARGET_XL_COMPAT) Save
|
||||
Conform more closely to IBM XLC semantics
|
||||
|
||||
mrecip
|
||||
|
|
@ -208,23 +311,23 @@ Target Report RejectNegative Joined
|
|||
Generate software reciprocal divide and square root for better throughput.
|
||||
|
||||
mrecip-precision
|
||||
Target Report Mask(RECIP_PRECISION)
|
||||
Target Report Mask(RECIP_PRECISION) Save
|
||||
Assume that the reciprocal estimate instructions provide more accuracy.
|
||||
|
||||
mno-fp-in-toc
|
||||
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC)
|
||||
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
|
||||
Do not place floating point constants in TOC
|
||||
|
||||
mfp-in-toc
|
||||
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0)
|
||||
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
|
||||
Place floating point constants in TOC
|
||||
|
||||
mno-sum-in-toc
|
||||
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC)
|
||||
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
|
||||
Do not place symbol+offset constants in TOC
|
||||
|
||||
msum-in-toc
|
||||
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0)
|
||||
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
|
||||
Place symbol+offset constants in TOC
|
||||
|
||||
; Output only one TOC entry per module. Normally linking fails if
|
||||
|
|
@ -243,7 +346,7 @@ Target Report
|
|||
Put everything in the regular TOC
|
||||
|
||||
mvrsave
|
||||
Target Report Var(TARGET_ALTIVEC_VRSAVE)
|
||||
Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
|
||||
Generate VRSAVE instructions when generating AltiVec code
|
||||
|
||||
mvrsave=
|
||||
|
|
@ -251,11 +354,11 @@ Target RejectNegative Joined
|
|||
-mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead
|
||||
|
||||
mblock-move-inline-limit=
|
||||
Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger
|
||||
Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
|
||||
Specify how many bytes should be moved inline before calling out to memcpy/memmove
|
||||
|
||||
misel
|
||||
Target Report Mask(ISEL)
|
||||
Target Report Mask(ISEL) Save
|
||||
Generate isel instructions
|
||||
|
||||
misel=
|
||||
|
|
@ -267,7 +370,7 @@ Target
|
|||
Generate SPE SIMD instructions on E500
|
||||
|
||||
mpaired
|
||||
Target Var(rs6000_paired_float)
|
||||
Target Var(rs6000_paired_float) Save
|
||||
Generate PPC750CL paired-single instructions
|
||||
|
||||
mspe=
|
||||
|
|
@ -295,19 +398,19 @@ Target RejectNegative Joined
|
|||
-mtraceback= Select full, part, or no traceback table
|
||||
|
||||
mlongcall
|
||||
Target Report Var(rs6000_default_long_calls)
|
||||
Target Report Var(rs6000_default_long_calls) Save
|
||||
Avoid all range limits on call instructions
|
||||
|
||||
mgen-cell-microcode
|
||||
Target Report Var(rs6000_gen_cell_microcode) Init(-1)
|
||||
Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
|
||||
Generate Cell microcode
|
||||
|
||||
mwarn-cell-microcode
|
||||
Target Var(rs6000_warn_cell_microcode) Init(0) Warning
|
||||
Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
|
||||
Warn when a Cell microcoded instruction is emitted
|
||||
|
||||
mwarn-altivec-long
|
||||
Target Var(rs6000_warn_altivec_long) Init(1)
|
||||
Target Var(rs6000_warn_altivec_long) Init(1) Save
|
||||
Warn about deprecated 'vector long ...' AltiVec type usage
|
||||
|
||||
mfloat-gprs=
|
||||
|
|
@ -331,19 +434,19 @@ Target RejectNegative Joined
|
|||
Specify alignment of structure fields default/natural
|
||||
|
||||
mprioritize-restricted-insns=
|
||||
Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority)
|
||||
Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
|
||||
Specify scheduling priority for dispatch slot restricted insns
|
||||
|
||||
msingle-float
|
||||
Target RejectNegative Var(rs6000_single_float)
|
||||
Target RejectNegative Var(rs6000_single_float) Save
|
||||
Single-precision floating point unit
|
||||
|
||||
mdouble-float
|
||||
Target RejectNegative Var(rs6000_double_float)
|
||||
Target RejectNegative Var(rs6000_double_float) Save
|
||||
Double-precision floating point unit
|
||||
|
||||
msimple-fpu
|
||||
Target RejectNegative Var(rs6000_simple_fpu)
|
||||
Target RejectNegative Var(rs6000_simple_fpu) Save
|
||||
Floating point unit does not support divide & sqrt
|
||||
|
||||
mfpu=
|
||||
|
|
@ -351,7 +454,7 @@ Target RejectNegative Joined
|
|||
-mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)
|
||||
|
||||
mxilinx-fpu
|
||||
Target Var(rs6000_xilinx_fpu)
|
||||
Target Var(rs6000_xilinx_fpu) Save
|
||||
Specify Xilinx FPU.
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -41,16 +41,6 @@
|
|||
#undef ASM_DEFAULT_SPEC
|
||||
#define ASM_DEFAULT_SPEC "-mppc"
|
||||
|
||||
/* Small data support types. */
|
||||
enum rs6000_sdata_type {
|
||||
SDATA_NONE, /* No small data support. */
|
||||
SDATA_DATA, /* Just put data in .sbss/.sdata, don't use relocs. */
|
||||
SDATA_SYSV, /* Use r13 to point to .sdata/.sbss. */
|
||||
SDATA_EABI /* Use r13 like above, r2 points to .sdata2/.sbss2. */
|
||||
};
|
||||
|
||||
extern enum rs6000_sdata_type rs6000_sdata;
|
||||
|
||||
#define TARGET_TOC ((target_flags & MASK_64BIT) \
|
||||
|| ((target_flags & (MASK_RELOCATABLE \
|
||||
| MASK_MINIMAL_TOC)) \
|
||||
|
|
@ -70,10 +60,6 @@ extern enum rs6000_sdata_type rs6000_sdata;
|
|||
#define TARGET_SECURE_PLT secure_plt
|
||||
#endif
|
||||
|
||||
extern const char *rs6000_abi_name;
|
||||
extern const char *rs6000_sdata_name;
|
||||
extern const char *rs6000_tls_size_string; /* For -mtls-size= */
|
||||
|
||||
#define SDATA_DEFAULT_SIZE 8
|
||||
|
||||
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ Target RejectNegative Joined
|
|||
Specify bit size of immediate TLS offsets
|
||||
|
||||
mbit-align
|
||||
Target Report Var(TARGET_NO_BITFIELD_TYPE)
|
||||
Target Report Var(TARGET_NO_BITFIELD_TYPE) Save
|
||||
Align to the base type of the bit-field
|
||||
|
||||
mstrict-align
|
||||
|
|
@ -74,7 +74,7 @@ Target RejectNegative
|
|||
no description yet
|
||||
|
||||
mprototype
|
||||
Target Var(target_prototype)
|
||||
Target Var(target_prototype) Save
|
||||
Assume all variable arg functions are prototyped
|
||||
|
||||
;; FIXME: Does nothing.
|
||||
|
|
@ -87,11 +87,11 @@ Target Report Mask(EABI)
|
|||
Use EABI
|
||||
|
||||
mbit-word
|
||||
Target Report Var(TARGET_NO_BITFIELD_WORD)
|
||||
Target Report Var(TARGET_NO_BITFIELD_WORD) Save
|
||||
Allow bit-fields to cross word boundaries
|
||||
|
||||
mregnames
|
||||
Target Var(rs6000_regnames)
|
||||
Target Var(rs6000_regnames) Save
|
||||
Use alternate register names
|
||||
|
||||
;; This option does nothing and only exists because the compiler
|
||||
|
|
@ -137,9 +137,9 @@ Target RejectNegative
|
|||
no description yet
|
||||
|
||||
msecure-plt
|
||||
Target Report RejectNegative Var(secure_plt, 1)
|
||||
Target Report RejectNegative Var(secure_plt, 1) Save
|
||||
Generate code to use a non-exec PLT and GOT
|
||||
|
||||
mbss-plt
|
||||
Target Report RejectNegative Var(secure_plt, 0)
|
||||
Target Report RejectNegative Var(secure_plt, 0) Save
|
||||
Generate code for old exec BSS PLT
|
||||
|
|
|
|||
19
gcc/configure
vendored
19
gcc/configure
vendored
|
|
@ -849,7 +849,8 @@ PACKAGE_TARNAME
|
|||
PACKAGE_NAME
|
||||
PATH_SEPARATOR
|
||||
SHELL'
|
||||
ac_subst_files='language_hooks'
|
||||
ac_subst_files='option_includes
|
||||
language_hooks'
|
||||
ac_user_opts='
|
||||
enable_option_checking
|
||||
with_build_libsubdir
|
||||
|
|
@ -10638,8 +10639,10 @@ fi
|
|||
|
||||
# Convert extra_options into a form suitable for Makefile use.
|
||||
extra_opt_files=
|
||||
all_opt_files=
|
||||
for f in $extra_options; do
|
||||
extra_opt_files="$extra_opt_files \$(srcdir)/config/$f"
|
||||
all_opt_files="$all_opt_files $srcdir/config/$f"
|
||||
done
|
||||
|
||||
|
||||
|
|
@ -17283,7 +17286,7 @@ else
|
|||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<_LT_EOF
|
||||
#line 17286 "configure"
|
||||
#line 17289 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
|
|
@ -17389,7 +17392,7 @@ else
|
|||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<_LT_EOF
|
||||
#line 17392 "configure"
|
||||
#line 17395 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
|
|
@ -25672,6 +25675,7 @@ do
|
|||
all_lang_makefrags="$all_lang_makefrags \$(srcdir)/$gcc_subdir/Make-lang.in"
|
||||
if test -f $srcdir/$gcc_subdir/lang.opt; then
|
||||
lang_opt_files="$lang_opt_files $srcdir/$gcc_subdir/lang.opt"
|
||||
all_opt_files="$all_opt_files $srcdir/$gcc_subdir/lang.opt"
|
||||
fi
|
||||
if test -f $srcdir/$gcc_subdir/$subdir-tree.def; then
|
||||
lang_tree_files="$lang_tree_files $srcdir/$gcc_subdir/$subdir-tree.def"
|
||||
|
|
@ -25723,6 +25727,14 @@ do
|
|||
echo "lang.$t: $x" >> Make-hooks
|
||||
done
|
||||
|
||||
# --------
|
||||
# Option include files
|
||||
# --------
|
||||
|
||||
${AWK} -f $srcdir/opt-include.awk $all_opt_files > option-includes.mk
|
||||
option_includes="option-includes.mk"
|
||||
|
||||
|
||||
# --------
|
||||
# UNSORTED
|
||||
# --------
|
||||
|
|
@ -27389,3 +27401,4 @@ if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then
|
|||
$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;}
|
||||
fi
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1382,8 +1382,10 @@ fi
|
|||
|
||||
# Convert extra_options into a form suitable for Makefile use.
|
||||
extra_opt_files=
|
||||
all_opt_files=
|
||||
for f in $extra_options; do
|
||||
extra_opt_files="$extra_opt_files \$(srcdir)/config/$f"
|
||||
all_opt_files="$all_opt_files $srcdir/config/$f"
|
||||
done
|
||||
AC_SUBST(extra_opt_files)
|
||||
|
||||
|
|
@ -4458,6 +4460,7 @@ changequote([,])dnl
|
|||
all_lang_makefrags="$all_lang_makefrags \$(srcdir)/$gcc_subdir/Make-lang.in"
|
||||
if test -f $srcdir/$gcc_subdir/lang.opt; then
|
||||
lang_opt_files="$lang_opt_files $srcdir/$gcc_subdir/lang.opt"
|
||||
all_opt_files="$all_opt_files $srcdir/$gcc_subdir/lang.opt"
|
||||
fi
|
||||
if test -f $srcdir/$gcc_subdir/$subdir-tree.def; then
|
||||
lang_tree_files="$lang_tree_files $srcdir/$gcc_subdir/$subdir-tree.def"
|
||||
|
|
@ -4507,6 +4510,14 @@ do
|
|||
echo "lang.$t: $x" >> Make-hooks
|
||||
done
|
||||
|
||||
# --------
|
||||
# Option include files
|
||||
# --------
|
||||
|
||||
${AWK} -f $srcdir/opt-include.awk $all_opt_files > option-includes.mk
|
||||
option_includes="option-includes.mk"
|
||||
AC_SUBST_FILE(option_includes)
|
||||
|
||||
# --------
|
||||
# UNSORTED
|
||||
# --------
|
||||
|
|
@ -4769,3 +4780,4 @@ done
|
|||
],
|
||||
[subdirs='$subdirs'])
|
||||
AC_OUTPUT
|
||||
|
||||
|
|
|
|||
|
|
@ -3272,6 +3272,8 @@ int core2_func (void) __attribute__ ((__target__ ("arch=core2")));
|
|||
int sse3_func (void) __attribute__ ((__target__ ("sse3")));
|
||||
@end smallexample
|
||||
|
||||
@table @samp
|
||||
@item i386 target attributes
|
||||
On the 386, the following options are allowed:
|
||||
|
||||
@table @samp
|
||||
|
|
@ -3414,19 +3416,195 @@ Specify which floating point unit to use. The
|
|||
@code{target("fpmath=sse,387")} option must be specified as
|
||||
@code{target("fpmath=sse+387")} because the comma would separate
|
||||
different options.
|
||||
|
||||
@item PowerPC target attributes
|
||||
On the PowerPC, the following options are allowed:
|
||||
|
||||
@table @samp
|
||||
@item altivec
|
||||
@itemx no-altivec
|
||||
@cindex @code{target("altivec")} attribute
|
||||
Generate code that uses (does not use) AltiVec instructions. In
|
||||
32-bit code, you cannot enable Altivec instructions unless
|
||||
@option{-mabi=altivec} was used on the command line.
|
||||
|
||||
@item cmpb
|
||||
@itemx no-cmpb
|
||||
@cindex @code{target("cmpb")} attribute
|
||||
Generate code that uses (does not use) the compare bytes instruction
|
||||
implemented on the POWER6 processor and other processors that support
|
||||
the PowerPC V2.05 architecture.
|
||||
|
||||
@item dlmzb
|
||||
@itemx no-dlmzb
|
||||
@cindex @code{target("dlmzb")} attribute
|
||||
Generate code that uses (does not use) the string-search @samp{dlmzb}
|
||||
instruction on the IBM 405, 440, 464 and 476 processors. This instruction is
|
||||
generated by default when targetting those processors.
|
||||
|
||||
@item fprnd
|
||||
@itemx no-fprnd
|
||||
@cindex @code{target("fprnd")} attribute
|
||||
Generate code that uses (does not use) the FP round to integer
|
||||
instructions implemented on the POWER5+ processor and other processors
|
||||
that support the PowerPC V2.03 architecture.
|
||||
|
||||
@item hard-dfp
|
||||
@itemx no-hard-dfp
|
||||
@cindex @code{target("hard-dfp")} attribute
|
||||
Generate code that uses (does not use) the decimal floating point
|
||||
instructions implemented on some POWER processors.
|
||||
|
||||
@item isel
|
||||
@itemx no-isel
|
||||
@cindex @code{target("isel")} attribute
|
||||
Generate code that uses (does not use) ISEL instruction.
|
||||
|
||||
@item mfcrf
|
||||
@itemx no-mfcrf
|
||||
@cindex @code{target("mfcrf")} attribute
|
||||
Generate code that uses (does not use) the move from condition
|
||||
register field instruction implemented on the POWER4 processor and
|
||||
other processors that support the PowerPC V2.01 architecture.
|
||||
|
||||
@item mfpgpr
|
||||
@itemx no-mfpgpr
|
||||
@cindex @code{target("mfpgpr")} attribute
|
||||
Generate code that uses (does not use) the FP move to/from general
|
||||
purpose register instructions implemented on the POWER6X processor and
|
||||
other processors that support the extended PowerPC V2.05 architecture.
|
||||
|
||||
@item mulhw
|
||||
@itemx no-mulhw
|
||||
@cindex @code{target("mulhw")} attribute
|
||||
Generate code that uses (does not use) the half-word multiply and
|
||||
multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.
|
||||
These instructions are generated by default when targetting those
|
||||
processors.
|
||||
|
||||
@item multiple
|
||||
@itemx no-multiple
|
||||
@cindex @code{target("multiple")} attribute
|
||||
Generate code that uses (does not use) the load multiple word
|
||||
instructions and the store multiple word instructions.
|
||||
|
||||
@item update
|
||||
@itemx no-update
|
||||
@cindex @code{target("update")} attribute
|
||||
Generate code that uses (does not use) the load or store instructions
|
||||
that update the base register to the address of the calculated memory
|
||||
location.
|
||||
|
||||
@item popcntb
|
||||
@itemx no-popcntb
|
||||
@cindex @code{target("popcntb")} attribute
|
||||
Generate code that uses (does not use) the popcount and double
|
||||
precision FP reciprocal estimate instruction implemented on the POWER5
|
||||
processor and other processors that support the PowerPC V2.02
|
||||
architecture.
|
||||
|
||||
@item popcntd
|
||||
@itemx no-popcntd
|
||||
@cindex @code{target("popcntd")} attribute
|
||||
Generate code that uses (does not use) the popcount instruction
|
||||
implemented on the POWER7 processor and other processors that support
|
||||
the PowerPC V2.06 architecture.
|
||||
|
||||
@item powerpc-gfxopt
|
||||
@itemx no-powerpc-gfxopt
|
||||
@cindex @code{target("powerpc-gfxopt")} attribute
|
||||
Generate code that uses (does not use) the optional PowerPC
|
||||
architecture instructions in the Graphics group, including
|
||||
floating-point select.
|
||||
|
||||
@item powerpc-gpopt
|
||||
@itemx no-powerpc-gpopt
|
||||
@cindex @code{target("powerpc-gpopt")} attribute
|
||||
Generate code that uses (does not use) the optional PowerPC
|
||||
architecture instructions in the General Purpose group, including
|
||||
floating-point square root.
|
||||
|
||||
@item recip-precision
|
||||
@itemx no-recip-precision
|
||||
@cindex @code{target("recip-precision")} attribute
|
||||
Assume (do not assume) that the reciprocal estimate instructions
|
||||
provide higher precision estimates than is mandated by the powerpc
|
||||
ABI.
|
||||
|
||||
@item string
|
||||
@itemx no-string
|
||||
@cindex @code{target("string")} attribute
|
||||
Generate code that uses (does not use) the load string instructions
|
||||
and the store string word instructions to save multiple registers and
|
||||
do small block moves.
|
||||
|
||||
@item vsx
|
||||
@itemx no-vsx
|
||||
@cindex @code{target("vsx")} attribute
|
||||
Generate code that uses (does not use) vector/scalar (VSX)
|
||||
instructions, and also enable the use of built-in functions that allow
|
||||
more direct access to the VSX instruction set. In 32-bit code, you
|
||||
cannot enable VSX or Altivec instructions unless
|
||||
@option{-mabi=altivec} was used on the command line.
|
||||
|
||||
@item friz
|
||||
@itemx no-friz
|
||||
@cindex @code{target("friz")} attribute
|
||||
Generate (do not generate) the @code{friz} instruction when the
|
||||
@option{-funsafe-math-optimizations} option is used to optimize
|
||||
rounding a floating point value to 64-bit integer and back to floating
|
||||
point. The @code{friz} instruction does not return the same value if
|
||||
the floating point number is too large to fit in an integer.
|
||||
|
||||
@item avoid-indexed-addresses
|
||||
@itemx no-avoid-indexed-addresses
|
||||
@cindex @code{target("avoid-indexed-addresses")} attribute
|
||||
Generate code that tries to avoid (not avoid) the use of indexed load
|
||||
or store instructions.
|
||||
|
||||
@item paired
|
||||
@itemx no-paired
|
||||
@cindex @code{target("paired")} attribute
|
||||
Generate code that uses (does not use) the generation of PAIRED simd
|
||||
instructions.
|
||||
|
||||
@item longcall
|
||||
@itemx no-longcall
|
||||
@cindex @code{target("longcall")} attribute
|
||||
Generate code that assumes (does not assume) that all calls are far
|
||||
away so that a longer more expensive calling sequence is required.
|
||||
|
||||
@item cpu=@var{CPU}
|
||||
@cindex @code{target("cpu=@var{CPU}")} attribute
|
||||
Specify the architecture to generate code for in compiling the
|
||||
function. If you select @code{"target("cpu=power7)"} attribute when
|
||||
generating 32-bit code, VSX and Altivec instructions are not generated
|
||||
unless you use the @option{-mabi=altivec} option on the command line.
|
||||
|
||||
@item tune=@var{TUNE}
|
||||
@cindex @code{target("tune=@var{TUNE}")} attribute
|
||||
Specify the architecture to tune for in compiling the function. If
|
||||
you do not specify the @code{target("tune=@var{TUNE}")} attribute and
|
||||
you do specifiy the @code{target("cpu=@var{CPU}")} attribute,
|
||||
compilation will tune for the @var{CPU} architecture, and not the
|
||||
default tuning specified on the command line.
|
||||
@end table
|
||||
@end table
|
||||
@end table
|
||||
|
||||
On the 386, you can use either multiple strings to specify multiple
|
||||
options, or you can separate the option with a comma (@code{,}).
|
||||
On the 386/x86_64 and PowerPC backends, you can use either multiple
|
||||
strings to specify multiple options, or you can separate the option
|
||||
with a comma (@code{,}).
|
||||
|
||||
On the 386, the inliner will not inline a function that has different
|
||||
target options than the caller, unless the callee has a subset of the
|
||||
target options of the caller. For example a function declared with
|
||||
@code{target("sse3")} can inline a function with
|
||||
@code{target("sse2")}, since @code{-msse3} implies @code{-msse2}.
|
||||
On the 386/x86_64 and PowerPC backends, the inliner will not inline a
|
||||
function that has different target options than the caller, unless the
|
||||
callee has a subset of the target options of the caller. For example
|
||||
a function declared with @code{target("sse3")} can inline a function
|
||||
with @code{target("sse2")}, since @code{-msse3} implies @code{-msse2}.
|
||||
|
||||
The @code{target} attribute is not implemented in GCC versions earlier
|
||||
than 4.4, and at present only the 386 uses it.
|
||||
than 4.4 for the i386/x86_64 and 4.6 for the PowerPC backends. It is
|
||||
not currently implemented for other backends.
|
||||
|
||||
@item tiny_data
|
||||
@cindex tiny data section on the H8/300H and H8S
|
||||
|
|
@ -13001,9 +13179,9 @@ function. The parenthesis around the options is optional.
|
|||
@xref{Function Attributes}, for more information about the
|
||||
@code{target} attribute and the attribute syntax.
|
||||
|
||||
The @samp{#pragma GCC target} pragma is not implemented in GCC
|
||||
versions earlier than 4.4, and is currently only implemented for the
|
||||
386 and x86_64 backends.
|
||||
The @code{#pragma GCC target} attribute is not implemented in GCC versions earlier
|
||||
than 4.4 for the i386/x86_64 and 4.6 for the PowerPC backends. At
|
||||
present, it is not implemented for other backends.
|
||||
@end table
|
||||
|
||||
@table @code
|
||||
|
|
|
|||
|
|
@ -15614,8 +15614,11 @@ is enabled by default when targetting Power6 and disabled otherwise.
|
|||
@opindex mfused-madd
|
||||
@opindex mno-fused-madd
|
||||
Generate code that uses (does not use) the floating point multiply and
|
||||
accumulate instructions. These instructions are generated by default if
|
||||
hardware floating is used.
|
||||
accumulate instructions. These instructions are generated by default
|
||||
if hardware floating point is used. The machine dependent
|
||||
@option{-mfused-madd} option is now mapped to the machine independent
|
||||
@option{-ffp-contract=fast} option, and @option{-mno-fused-madd} is
|
||||
mapped to @option{-ffp-contract=off}.
|
||||
|
||||
@item -mmulhw
|
||||
@itemx -mno-mulhw
|
||||
|
|
|
|||
|
|
@ -51,6 +51,32 @@ record, or duplicating it in many records, would be inappropriate, or
|
|||
for variables set in option handlers rather than referenced by
|
||||
@code{Var} properties.
|
||||
|
||||
@item
|
||||
A variable record to define a variable used to store option
|
||||
information. These records have two fields: the string
|
||||
@samp{TargetVariable}, and a declaration of the type and name of the
|
||||
variable, optionally with an initializer (but without any trailing
|
||||
@samp{;}). @samp{TargetVariable} is a combination of @samp{Variable}
|
||||
and @samp{TargetSave} records in that the variable is defined in the
|
||||
@code{gcc_options} structure, but these variables are also stored in
|
||||
the @code{cl_target_option} structure. The variables are saved in the
|
||||
target save code and restored in the target restore code.
|
||||
|
||||
@item
|
||||
A variable record to record any additional files that the
|
||||
@file{options.h} file should include. This is useful to provide
|
||||
enumeration or structure definitions needed for target variables.
|
||||
These records have two fields: the string @samp{HeaderInclude} and the
|
||||
name of the include file.
|
||||
|
||||
@item
|
||||
A variable record to record any additional files that the
|
||||
@file{options.c} file should include. This is useful to provide
|
||||
inline functions needed for target variables and/or @code{#ifdef}
|
||||
sequences to properly set up the initialization. These records have
|
||||
two fields: the string @samp{SourceInclude} and the name of the
|
||||
include file.
|
||||
|
||||
@item
|
||||
An option definition record. These records have the following fields:
|
||||
@enumerate
|
||||
|
|
|
|||
30
gcc/opt-include.awk
Normal file
30
gcc/opt-include.awk
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
# Copyright (C) 2010
|
||||
# Free Software Foundation, Inc.
|
||||
# Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the
|
||||
# Free Software Foundation; either version 3, or (at your option) any
|
||||
# later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
# This Awk script reads in the option records and emits the include files
|
||||
# listed by the HeaderInclude directive.
|
||||
|
||||
BEGIN {
|
||||
h_next = 0
|
||||
c_next = 0
|
||||
}
|
||||
|
||||
(h_next != 0) { print "OPTIONS_H_EXTRA += $(srcdir)/" $1; h_next = 0 }
|
||||
(c_next != 0) { print "OPTIONS_C_EXTRA += $(srcdir)/" $1; c_next = 0 }
|
||||
/^HeaderInclude$/ { h_next = 1; c_next = 0 }
|
||||
/^SourceInclude$/ { h_next = 0; c_next = 1 }
|
||||
|
|
@ -31,7 +31,10 @@ BEGIN {
|
|||
n_langs = 0
|
||||
n_target_save = 0
|
||||
n_extra_vars = 0
|
||||
quote = "\042"
|
||||
n_extra_target_vars = 0
|
||||
n_extra_c_includes = 0
|
||||
n_extra_h_includes = 0
|
||||
quote = "\042"
|
||||
comma = ","
|
||||
FS=SUBSEP
|
||||
# Default the name of header created from opth-gen.awk to options.h
|
||||
|
|
@ -53,6 +56,30 @@ BEGIN {
|
|||
extra_vars[n_extra_vars] = $2
|
||||
n_extra_vars++
|
||||
}
|
||||
else if ($1 == "TargetVariable") {
|
||||
# Combination of TargetSave and Variable
|
||||
extra_vars[n_extra_vars] = $2
|
||||
n_extra_vars++
|
||||
|
||||
var = $2
|
||||
sub(" *=.*", "", var)
|
||||
orig_var = var
|
||||
name = var
|
||||
type = var
|
||||
sub("^.*[ *]", "", name)
|
||||
sub(" *" name "$", "", type)
|
||||
target_save_decl[n_target_save] = type " x_" name
|
||||
n_target_save++
|
||||
|
||||
extra_target_vars[n_extra_target_vars] = name
|
||||
n_extra_target_vars++;
|
||||
}
|
||||
else if ($1 == "HeaderInclude") {
|
||||
extra_h_includes[n_extra_h_includes++] = $2;
|
||||
}
|
||||
else if ($1 == "SourceInclude") {
|
||||
extra_c_includes[n_extra_c_includes++] = $2;
|
||||
}
|
||||
else {
|
||||
name = opt_args("Mask", $1)
|
||||
if (name == "") {
|
||||
|
|
@ -82,7 +109,17 @@ print "#include " quote "target.h" quote
|
|||
print "#endif /* GCC_DRIVER */"
|
||||
print ""
|
||||
|
||||
if (n_extra_c_includes > 0) {
|
||||
for (i = 0; i < n_extra_c_includes; i++) {
|
||||
print "#include " quote extra_c_includes[i] quote
|
||||
}
|
||||
print ""
|
||||
}
|
||||
|
||||
have_save = 0;
|
||||
if (n_extra_target_vars)
|
||||
have_save = 1
|
||||
|
||||
print "const struct gcc_options global_options_init =\n{"
|
||||
for (i = 0; i < n_extra_vars; i++) {
|
||||
var = extra_vars[i]
|
||||
|
|
@ -305,11 +342,13 @@ print "{";
|
|||
n_opt_char = 2;
|
||||
n_opt_short = 0;
|
||||
n_opt_int = 0;
|
||||
n_opt_enum = 1;
|
||||
n_opt_other = 0;
|
||||
var_opt_char[0] = "optimize";
|
||||
var_opt_char[1] = "optimize_size";
|
||||
var_opt_range["optimize"] = "0, 255";
|
||||
var_opt_range["optimize_size"] = "0, 255";
|
||||
var_opt_enum[0] = "flag_fp_contract_mode";
|
||||
|
||||
# Sort by size to mimic how the structure is laid out to be friendlier to the
|
||||
# cache.
|
||||
|
|
@ -331,6 +370,9 @@ for (i = 0; i < n_opts; i++) {
|
|||
else if (otype ~ "^((un)?signed +)?short *$")
|
||||
var_opt_short[n_opt_short++] = name;
|
||||
|
||||
else if (otype ~ ("^enum +[_" alnum "]+ *"))
|
||||
var_opt_enum[n_opt_enum++] = name;
|
||||
|
||||
else if (otype ~ "^((un)?signed +)?char *$") {
|
||||
var_opt_char[n_opt_char++] = name;
|
||||
if (otype ~ "^unsigned +char *$")
|
||||
|
|
@ -358,6 +400,10 @@ for (i = 0; i < n_opt_int; i++) {
|
|||
print " ptr->x_" var_opt_int[i] " = opts->x_" var_opt_int[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_opt_enum; i++) {
|
||||
print " ptr->x_" var_opt_enum[i] " = opts->x_" var_opt_enum[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_opt_short; i++) {
|
||||
print " ptr->x_" var_opt_short[i] " = opts->x_" var_opt_short[i] ";";
|
||||
}
|
||||
|
|
@ -382,6 +428,10 @@ for (i = 0; i < n_opt_int; i++) {
|
|||
print " opts->x_" var_opt_int[i] " = ptr->x_" var_opt_int[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_opt_enum; i++) {
|
||||
print " opts->x_" var_opt_enum[i] " = ptr->x_" var_opt_enum[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_opt_short; i++) {
|
||||
print " opts->x_" var_opt_short[i] " = ptr->x_" var_opt_short[i] ";";
|
||||
}
|
||||
|
|
@ -420,6 +470,14 @@ for (i = 0; i < n_opt_int; i++) {
|
|||
print "";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_opt_enum; i++) {
|
||||
print " fprintf (file, \"%*s%s (%#x)\\n\",";
|
||||
print " indent_to, \"\",";
|
||||
print " \"" var_opt_enum[i] "\",";
|
||||
print " (int) ptr->x_" var_opt_enum[i] ");";
|
||||
print "";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_opt_short; i++) {
|
||||
print " if (ptr->x_" var_opt_short[i] ")";
|
||||
print " fprintf (file, \"%*s%s (%#x)\\n\",";
|
||||
|
|
@ -449,6 +507,7 @@ print "{";
|
|||
n_target_char = 0;
|
||||
n_target_short = 0;
|
||||
n_target_int = 0;
|
||||
n_target_enum = 0;
|
||||
n_target_other = 0;
|
||||
|
||||
if (have_save) {
|
||||
|
|
@ -469,6 +528,9 @@ if (have_save) {
|
|||
else if (otype ~ "^((un)?signed +)?short *$")
|
||||
var_target_short[n_target_short++] = name;
|
||||
|
||||
else if (otype ~ ("^enum +[_" alnum "]+ *$"))
|
||||
var_target_enum[n_target_enum++] = name;
|
||||
|
||||
else if (otype ~ "^((un)?signed +)?char *$") {
|
||||
var_target_char[n_target_char++] = name;
|
||||
if (otype ~ "^unsigned +char *$")
|
||||
|
|
@ -500,10 +562,18 @@ print " if (targetm.target_option.save)";
|
|||
print " targetm.target_option.save (ptr);";
|
||||
print "";
|
||||
|
||||
for (i = 0; i < n_extra_target_vars; i++) {
|
||||
print " ptr->x_" extra_target_vars[i] " = opts->x_" extra_target_vars[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_other; i++) {
|
||||
print " ptr->x_" var_target_other[i] " = opts->x_" var_target_other[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_enum; i++) {
|
||||
print " ptr->x_" var_target_enum[i] " = opts->x_" var_target_enum[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_int; i++) {
|
||||
print " ptr->x_" var_target_int[i] " = opts->x_" var_target_int[i] ";";
|
||||
}
|
||||
|
|
@ -524,10 +594,18 @@ print "void";
|
|||
print "cl_target_option_restore (struct gcc_options *opts, struct cl_target_option *ptr)";
|
||||
print "{";
|
||||
|
||||
for (i = 0; i < n_extra_target_vars; i++) {
|
||||
print " opts->x_" extra_target_vars[i] " = ptr->x_" extra_target_vars[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_other; i++) {
|
||||
print " opts->x_" var_target_other[i] " = ptr->x_" var_target_other[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_enum; i++) {
|
||||
print " opts->x_" var_target_enum[i] " = ptr->x_" var_target_enum[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_int; i++) {
|
||||
print " opts->x_" var_target_int[i] " = ptr->x_" var_target_int[i] ";";
|
||||
}
|
||||
|
|
@ -566,6 +644,15 @@ for (i = 0; i < n_target_other; i++) {
|
|||
print "";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_enum; i++) {
|
||||
print " if (ptr->x_" var_target_enum[i] ")";
|
||||
print " fprintf (file, \"%*s%s (%#x)\\n\",";
|
||||
print " indent, \"\",";
|
||||
print " \"" var_target_enum[i] "\",";
|
||||
print " ptr->x_" var_target_enum[i] ");";
|
||||
print "";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_int; i++) {
|
||||
print " if (ptr->x_" var_target_int[i] ")";
|
||||
print " fprintf (file, \"%*s%s (%#x)\\n\",";
|
||||
|
|
|
|||
|
|
@ -29,7 +29,12 @@ BEGIN {
|
|||
n_langs = 0
|
||||
n_target_save = 0
|
||||
n_extra_vars = 0
|
||||
n_extra_target_vars = 0
|
||||
n_extra_masks = 0
|
||||
n_extra_c_includes = 0
|
||||
n_extra_h_includes = 0
|
||||
have_save = 0;
|
||||
quote = "\042"
|
||||
FS=SUBSEP
|
||||
}
|
||||
|
||||
|
|
@ -48,6 +53,30 @@ BEGIN {
|
|||
extra_vars[n_extra_vars] = $2
|
||||
n_extra_vars++
|
||||
}
|
||||
else if ($1 == "TargetVariable") {
|
||||
# Combination of TargetSave and Variable
|
||||
extra_vars[n_extra_vars] = $2
|
||||
n_extra_vars++
|
||||
|
||||
var = $2
|
||||
sub(" *=.*", "", var)
|
||||
orig_var = var
|
||||
name = var
|
||||
type = var
|
||||
sub("^.*[ *]", "", name)
|
||||
sub(" *" name "$", "", type)
|
||||
target_save_decl[n_target_save] = type " x_" name
|
||||
n_target_save++
|
||||
|
||||
extra_target_vars[n_extra_target_vars] = name
|
||||
n_extra_target_vars++
|
||||
}
|
||||
else if ($1 == "HeaderInclude") {
|
||||
extra_h_includes[n_extra_h_includes++] = $2;
|
||||
}
|
||||
else if ($1 == "SourceInclude") {
|
||||
extra_c_includes[n_extra_c_includes++] = $2;
|
||||
}
|
||||
else {
|
||||
name = opt_args("Mask", $1)
|
||||
if (name == "") {
|
||||
|
|
@ -73,11 +102,21 @@ print ""
|
|||
print "#include \"flag-types.h\""
|
||||
print ""
|
||||
|
||||
have_save = 0;
|
||||
if (n_extra_h_includes > 0) {
|
||||
for (i = 0; i < n_extra_h_includes; i++) {
|
||||
print "#include " quote extra_h_includes[i] quote
|
||||
}
|
||||
print ""
|
||||
}
|
||||
|
||||
print "#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)"
|
||||
print "#ifndef GENERATOR_FILE"
|
||||
print "struct gcc_options\n{"
|
||||
print "#if !defined(GCC_DRIVER) && !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS)"
|
||||
print "struct GTY(()) gcc_options"
|
||||
print "#else"
|
||||
print "struct gcc_options"
|
||||
print "#endif"
|
||||
print "{"
|
||||
print "#endif"
|
||||
|
||||
for (i = 0; i < n_extra_vars; i++) {
|
||||
|
|
@ -155,9 +194,11 @@ print "{";
|
|||
n_opt_char = 2;
|
||||
n_opt_short = 0;
|
||||
n_opt_int = 0;
|
||||
n_opt_enum = 1;
|
||||
n_opt_other = 0;
|
||||
var_opt_char[0] = "unsigned char x_optimize";
|
||||
var_opt_char[1] = "unsigned char x_optimize_size";
|
||||
var_opt_enum[0] = "enum fp_contract_mode x_flag_fp_contract_mode";
|
||||
|
||||
for (i = 0; i < n_opts; i++) {
|
||||
if (flag_set_p("Optimization", flags[i])) {
|
||||
|
|
@ -179,6 +220,9 @@ for (i = 0; i < n_opts; i++) {
|
|||
else if (otype ~ "^((un)?signed +)?char *$")
|
||||
var_opt_char[n_opt_char++] = otype "x_" name;
|
||||
|
||||
else if (otype ~ ("^enum +[_" alnum "]+ *$"))
|
||||
var_opt_enum[n_opt_enum++] = otype "x_" name;
|
||||
|
||||
else
|
||||
var_opt_other[n_opt_other++] = otype "x_" name;
|
||||
}
|
||||
|
|
@ -192,6 +236,10 @@ for (i = 0; i < n_opt_int; i++) {
|
|||
print " " var_opt_int[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_opt_enum; i++) {
|
||||
print " " var_opt_enum[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_opt_short; i++) {
|
||||
print " " var_opt_short[i] ";";
|
||||
}
|
||||
|
|
@ -211,6 +259,7 @@ print "{";
|
|||
n_target_char = 0;
|
||||
n_target_short = 0;
|
||||
n_target_int = 0;
|
||||
n_target_enum = 0;
|
||||
n_target_other = 0;
|
||||
|
||||
for (i = 0; i < n_target_save; i++) {
|
||||
|
|
@ -223,6 +272,9 @@ for (i = 0; i < n_target_save; i++) {
|
|||
else if (target_save_decl[i] ~ "^((un)?signed +)?char +[_ " alnum "]+$")
|
||||
var_target_char[n_target_char++] = target_save_decl[i];
|
||||
|
||||
else if (target_save_decl[i] ~ ("^enum +[_" alnum "]+ +[_" alnum "]+$")) {
|
||||
var_target_enum[n_target_enum++] = target_save_decl[i];
|
||||
}
|
||||
else
|
||||
var_target_other[n_target_other++] = target_save_decl[i];
|
||||
}
|
||||
|
|
@ -248,6 +300,9 @@ if (have_save) {
|
|||
else if (otype ~ "^((un)?signed +)?char *$")
|
||||
var_target_char[n_target_char++] = otype "x_" name;
|
||||
|
||||
else if (otype ~ ("^enum +[_" alnum "]+ +[_" alnum "]+"))
|
||||
var_target_enum[n_target_enum++] = otype "x_" name;
|
||||
|
||||
else
|
||||
var_target_other[n_target_other++] = otype "x_" name;
|
||||
}
|
||||
|
|
@ -260,6 +315,10 @@ for (i = 0; i < n_target_other; i++) {
|
|||
print " " var_target_other[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_enum; i++) {
|
||||
print " " var_target_enum[i] ";";
|
||||
}
|
||||
|
||||
for (i = 0; i < n_target_int; i++) {
|
||||
print " " var_target_int[i] ";";
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,10 @@
|
|||
2010-11-19 Michael Meissner <meissner@linux.vnet.ibm.com>
|
||||
|
||||
* gcc.target/powerpc/ppc-target-1.c: New file to test target
|
||||
attributes on PowerPC.
|
||||
* gcc.target/powerpc/ppc-target-2.c: Ditto.
|
||||
* gcc.target/powerpc/ppc-target-3.c: Ditto.
|
||||
|
||||
2010-11-19 Nicola Pero <nicola.pero@meta-innovation.com>
|
||||
|
||||
* objc.dg/attributes/proto-attribute-1.m: Updated.
|
||||
|
|
|
|||
59
gcc/testsuite/gcc.target/powerpc/ppc-target-1.c
Normal file
59
gcc/testsuite/gcc.target/powerpc/ppc-target-1.c
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/* { dg-do compile { target { powerpc*-*-* } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_vsx_ok } */
|
||||
/* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=altivec" } */
|
||||
/* { dg-final { scan-assembler-times "fabs" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "fnabs" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "fsel" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */
|
||||
|
||||
double normal1 (double, double);
|
||||
double power5 (double, double) __attribute__((__target__("cpu=power5")));
|
||||
double power6 (double, double) __attribute__((__target__("cpu=power6")));
|
||||
double power6x (double, double) __attribute__((__target__("cpu=power6x")));
|
||||
double power7 (double, double) __attribute__((__target__("cpu=power7")));
|
||||
double power7n (double, double) __attribute__((__target__("cpu=power7,no-vsx")));
|
||||
double normal2 (double, double);
|
||||
|
||||
/* fabs/fnabs/fsel */
|
||||
double normal1 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fabs/fnabs/fsel */
|
||||
double power5 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fcpsgn */
|
||||
double power6 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fcpsgn */
|
||||
double power6x (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* xscpsgndp */
|
||||
double power7 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fcpsgn */
|
||||
double power7n (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fabs/fnabs/fsel */
|
||||
double normal2 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
41
gcc/testsuite/gcc.target/powerpc/ppc-target-2.c
Normal file
41
gcc/testsuite/gcc.target/powerpc/ppc-target-2.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/* { dg-do compile { target { powerpc*-*-* } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_vsx_ok } */
|
||||
/* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=altivec" } */
|
||||
/* { dg-final { scan-assembler-times "fabs" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "fnabs" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "fsel" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */
|
||||
|
||||
/* fabs/fnabs/fsel */
|
||||
double normal1 (double a, double b) { return __builtin_copysign (a, b); }
|
||||
|
||||
#pragma GCC push_options
|
||||
#pragma GCC target ("cpu=power5")
|
||||
/* fabs/fnabs/fsel */
|
||||
double power5 (double a, double b) { return __builtin_copysign (a, b); }
|
||||
#pragma GCC pop_options
|
||||
|
||||
#pragma GCC target ("cpu=power6")
|
||||
/* fcpsgn */
|
||||
double power6 (double a, double b) { return __builtin_copysign (a, b); }
|
||||
#pragma GCC reset_options
|
||||
|
||||
#pragma GCC target ("cpu=power6x")
|
||||
/* fcpsgn */
|
||||
double power6x (double a, double b) { return __builtin_copysign (a, b); }
|
||||
#pragma GCC reset_options
|
||||
|
||||
#pragma GCC target ("cpu=power7")
|
||||
/* xscpsgndp */
|
||||
double power7 (double a, double b) { return __builtin_copysign (a, b); }
|
||||
#pragma GCC reset_options
|
||||
|
||||
#pragma GCC target ("cpu=power7,no-vsx")
|
||||
/* fcpsgn */
|
||||
double power7n (double a, double b) { return __builtin_copysign (a, b); }
|
||||
#pragma GCC reset_options
|
||||
|
||||
/* fabs/fnabs/fsel */
|
||||
double normal2 (double a, double b) { return __builtin_copysign (a, b); }
|
||||
62
gcc/testsuite/gcc.target/powerpc/ppc-target-3.c
Normal file
62
gcc/testsuite/gcc.target/powerpc/ppc-target-3.c
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_vsx_ok } */
|
||||
/* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=no-altivec" } */
|
||||
/* { dg-final { scan-assembler-times "fabs" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "fnabs" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "fsel" 3 } } */
|
||||
/* { dg-final { scan-assembler-times "fcpsgn" 4 } } */
|
||||
/* { dg-final { scan-assembler-not "xscpsgndp" } } */
|
||||
|
||||
/* Like ppc-target-1.c, but do not enable the altivec abi on 32-bit, so the
|
||||
power7 code should generate fcpsgn and not xscpsgndp. */
|
||||
|
||||
double normal1 (double, double);
|
||||
double power5 (double, double) __attribute__((__target__("cpu=power5")));
|
||||
double power6 (double, double) __attribute__((__target__("cpu=power6")));
|
||||
double power6x (double, double) __attribute__((__target__("cpu=power6x")));
|
||||
double power7 (double, double) __attribute__((__target__("cpu=power7")));
|
||||
double power7n (double, double) __attribute__((__target__("cpu=power7,no-vsx")));
|
||||
double normal2 (double, double);
|
||||
|
||||
/* fabs/fnabs/fsel */
|
||||
double normal1 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fabs/fnabs/fsel */
|
||||
double power5 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fcpsgn */
|
||||
double power6 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fcpsgn */
|
||||
double power6x (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* xscpsgndp */
|
||||
double power7 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fcpsgn */
|
||||
double power7n (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
|
||||
/* fabs/fnabs/fsel */
|
||||
double normal2 (double a, double b)
|
||||
{
|
||||
return __builtin_copysign (a, b);
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue