linux-atomic.c (__kernel_cmpxchg): Reorder arguments to better match light-weight syscall argument order.
* config/pa/linux-atomic.c (__kernel_cmpxchg): Reorder arguments to better match light-weight syscall argument order. (__kernel_cmpxchg2): Likewise. Adjust callers. From-SVN: r225267
This commit is contained in:
John David Anglin
parent
5747290f51
commit
f9a12f7b8f
2 changed files with 33 additions and 26 deletions
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@ -1,3 +1,10 @@
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2015-07-01 John David Anglin <danglin@gcc.gnu.org>
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* config/pa/linux-atomic.c (__kernel_cmpxchg): Reorder arguments to
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better match light-weight syscall argument order.
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(__kernel_cmpxchg2): Likewise.
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Adjust callers.
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2015-06-30 H.J. Lu <hongjiu.lu@intel.com>
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* config.host: Support i[34567]86-*-elfiamcu target.
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@ -46,18 +46,17 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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/* Kernel helper for compare-and-exchange a 32-bit value. */
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static inline long
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__kernel_cmpxchg (int oldval, int newval, int *mem)
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__kernel_cmpxchg (int *mem, int oldval, int newval)
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{
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register unsigned long lws_mem asm("r26") = (unsigned long) (mem);
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register long lws_ret asm("r28");
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register long lws_errno asm("r21");
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register int lws_old asm("r25") = oldval;
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register int lws_new asm("r24") = newval;
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register long lws_ret asm("r28");
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register long lws_errno asm("r21");
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asm volatile ( "ble 0xb0(%%sr2, %%r0) \n\t"
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"ldi %5, %%r20 \n\t"
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: "=r" (lws_ret), "=r" (lws_errno), "=r" (lws_mem),
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"=r" (lws_old), "=r" (lws_new)
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: "i" (LWS_CAS), "2" (lws_mem), "3" (lws_old), "4" (lws_new)
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"ldi %2, %%r20 \n\t"
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: "=r" (lws_ret), "=r" (lws_errno)
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: "i" (LWS_CAS), "r" (lws_mem), "r" (lws_old), "r" (lws_new)
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: "r1", "r20", "r22", "r23", "r29", "r31", "memory"
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);
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if (__builtin_expect (lws_errno == -EFAULT || lws_errno == -ENOSYS, 0))
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@ -73,19 +72,20 @@ __kernel_cmpxchg (int oldval, int newval, int *mem)
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}
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static inline long
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__kernel_cmpxchg2 (const void *oldval, const void *newval, void *mem,
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__kernel_cmpxchg2 (void *mem, const void *oldval, const void *newval,
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int val_size)
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{
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register unsigned long lws_mem asm("r26") = (unsigned long) (mem);
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register long lws_ret asm("r28");
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register long lws_errno asm("r21");
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register unsigned long lws_old asm("r25") = (unsigned long) oldval;
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register unsigned long lws_new asm("r24") = (unsigned long) newval;
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register int lws_size asm("r23") = val_size;
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register long lws_ret asm("r28");
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register long lws_errno asm("r21");
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asm volatile ( "ble 0xb0(%%sr2, %%r0) \n\t"
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"ldi %2, %%r20 \n\t"
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: "=r" (lws_ret), "=r" (lws_errno)
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: "i" (2), "r" (lws_mem), "r" (lws_old), "r" (lws_new), "r" (lws_size)
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"ldi %6, %%r20 \n\t"
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: "=r" (lws_ret), "=r" (lws_errno), "+r" (lws_mem),
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"+r" (lws_old), "+r" (lws_new), "+r" (lws_size)
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: "i" (2)
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: "r1", "r20", "r22", "r29", "r31", "fr4", "memory"
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);
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if (__builtin_expect (lws_errno == -EFAULT || lws_errno == -ENOSYS, 0))
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@ -116,7 +116,7 @@ __kernel_cmpxchg2 (const void *oldval, const void *newval, void *mem,
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do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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newval = PFX_OP (tmp INF_OP val); \
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failure = __kernel_cmpxchg2 (&tmp, &newval, ptr, INDEX); \
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failure = __kernel_cmpxchg2 (ptr, &tmp, &newval, INDEX); \
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} while (failure != 0); \
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\
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return tmp; \
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@ -146,7 +146,7 @@ FETCH_AND_OP_2 (nand, ~, &, signed char, 1, 0)
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do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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newval = PFX_OP (tmp INF_OP val); \
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failure = __kernel_cmpxchg2 (&tmp, &newval, ptr, INDEX); \
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failure = __kernel_cmpxchg2 (ptr, &tmp, &newval, INDEX); \
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} while (failure != 0); \
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\
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return PFX_OP (tmp INF_OP val); \
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@ -174,7 +174,7 @@ OP_AND_FETCH_2 (nand, ~, &, signed char, 1, 0)
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\
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do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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failure = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr); \
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failure = __kernel_cmpxchg (ptr, tmp, PFX_OP (tmp INF_OP val)); \
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} while (failure != 0); \
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\
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return tmp; \
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@ -195,7 +195,7 @@ FETCH_AND_OP_WORD (nand, ~, &)
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\
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do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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failure = __kernel_cmpxchg (tmp, PFX_OP (tmp INF_OP val), ptr); \
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failure = __kernel_cmpxchg (ptr, tmp, PFX_OP (tmp INF_OP val)); \
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} while (failure != 0); \
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\
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return PFX_OP (tmp INF_OP val); \
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@ -225,7 +225,7 @@ typedef unsigned char bool;
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if (__builtin_expect (oldval != actual_oldval, 0)) \
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return actual_oldval; \
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\
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fail = __kernel_cmpxchg2 (&actual_oldval, &newval, ptr, INDEX); \
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fail = __kernel_cmpxchg2 (ptr, &actual_oldval, &newval, INDEX); \
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\
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if (__builtin_expect (!fail, 1)) \
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return actual_oldval; \
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@ -236,7 +236,7 @@ typedef unsigned char bool;
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__sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \
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TYPE newval) \
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{ \
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int failure = __kernel_cmpxchg2 (&oldval, &newval, ptr, INDEX); \
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int failure = __kernel_cmpxchg2 (ptr, &oldval, &newval, INDEX); \
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return (failure != 0); \
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}
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@ -255,7 +255,7 @@ __sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval)
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if (__builtin_expect (oldval != actual_oldval, 0))
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return actual_oldval;
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fail = __kernel_cmpxchg (actual_oldval, newval, ptr);
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fail = __kernel_cmpxchg (ptr, actual_oldval, newval);
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if (__builtin_expect (!fail, 1))
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return actual_oldval;
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@ -265,7 +265,7 @@ __sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval)
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bool HIDDEN
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__sync_bool_compare_and_swap_4 (int *ptr, int oldval, int newval)
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{
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int failure = __kernel_cmpxchg (oldval, newval, ptr);
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int failure = __kernel_cmpxchg (ptr, oldval, newval);
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return (failure == 0);
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}
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@ -278,7 +278,7 @@ TYPE HIDDEN \
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\
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do { \
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oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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failure = __kernel_cmpxchg2 (&oldval, &val, ptr, INDEX); \
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failure = __kernel_cmpxchg2 (ptr, &oldval, &val, INDEX); \
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} while (failure != 0); \
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\
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return oldval; \
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@ -294,7 +294,7 @@ __sync_lock_test_and_set_4 (int *ptr, int val)
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do {
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oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST);
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failure = __kernel_cmpxchg (oldval, val, ptr);
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failure = __kernel_cmpxchg (ptr, oldval, val);
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} while (failure != 0);
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return oldval;
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@ -308,7 +308,7 @@ __sync_lock_test_and_set_4 (int *ptr, int val)
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\
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do { \
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oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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failure = __kernel_cmpxchg2 (&oldval, &zero, ptr, INDEX); \
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failure = __kernel_cmpxchg2 (ptr, &oldval, &zero, INDEX); \
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} while (failure != 0); \
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}
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@ -321,7 +321,7 @@ __sync_lock_release_4 (int *ptr)
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int failure, oldval;
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do {
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oldval = *ptr;
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failure = __kernel_cmpxchg (oldval, 0, ptr);
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oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST);
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failure = __kernel_cmpxchg (ptr, oldval, 0);
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} while (failure != 0);
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}
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