FreeChainXenon/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

re PR rtl-optimization/17104 (Non-optimal code generation for bitfield initialization)

Browse source 
.:	PR rtl-optimization/17104
	* config/rs6000/rs6000.c (rs6000_emit_move): Don't wrap small
	loads in zero_extend.
testsuite:
	PR rtl-optimization/17104
	* gcc.dg/ppc-bitfield1.c: New.

From-SVN: r89980
This commit is contained in:
Nathan Sidwell 2004-11-02 09:50:35 +00:00 • committed by Nathan Sidwell
parent 8f49f0f199
commit f6219a5e9c
4 changed files with 80 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
gcc/ChangeLog
View file

@ -1,3 +1,9 @@
2004-11-02 Nathan Sidwell <nathan@codesourcery.com>
PR rtl-optimization/17104
* config/rs6000/rs6000.c (rs6000_emit_move): Don't wrap small
loads in zero_extend.
2004-11-02 Danny Smith <dannysmith@users.sourceforge.net>
PR debug/18242

18
gcc/config/rs6000/rs6000.c
View file

@ -4264,22 +4264,8 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
return;
}
if (!no_new_pseudos)
{
if (GET_CODE (operands[1]) == MEM && optimize > 0
&& (mode == QImode || mode == HImode || mode == SImode)
&& GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
{
rtx reg = gen_reg_rtx (word_mode);
emit_insn (gen_rtx_SET (word_mode, reg,
gen_rtx_ZERO_EXTEND (word_mode,
operands[1])));
operands[1] = gen_lowpart (mode, reg);
}
if (GET_CODE (operands[0]) != REG)
operands[1] = force_reg (mode, operands[1]);
}
if (!no_new_pseudos && GET_CODE (operands[0]) != REG)
operands[1] = force_reg (mode, operands[1]);
if (mode == SFmode && ! TARGET_POWERPC
&& TARGET_HARD_FLOAT && TARGET_FPRS

5
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2004-11-02 Nathan Sidwell <nathan@codesourcery.com>
PR rtl-optimization/17104
* gcc.dg/ppc-bitfield1.c: New.
2004-11-01 Richard Sandiford <rsandifo@redhat.com>
* gcc.dg/uninit-H.c (ASM): Define to "$sp" on MIPS targets.

67
gcc/testsuite/gcc.dg/ppc-bitfield1.c Normal file
View file

@ -0,0 +1,67 @@
/* { dg-do compile { target powerpc64-*-* } } */
/* { dg-options "-m64 -O2" } */
/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,1,31" } } */
/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,0xffffffff" } } */
/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
/* PR 17104 many sign extends added. */
struct {
int f1 : 1;
int f2 : 1;
int f3 : 1;
int f4 : 1;
int f5 : 1;
int f6 : 1;
int f7 : 1;
int f8 : 1;
int f9 : 1;
int f10 : 1;
int f11 : 1;
int f12 : 1;
int f13 : 1;
int f14 : 1;
int f15 : 1;
int f16 : 1;
int f17 : 2;
int f18 : 2;
int f19 : 2;
int f20 : 2;
int f21 : 2;
int f22 : 2;
int f23 : 2;
int f24 : 2;
} s;
void foo ()
{
s.f1 = 0;
s.f2 = 0;
s.f3 = 0;
s.f4 = 0;
s.f5 = 0;
s.f6 = 0;
s.f7 = 0;
s.f8 = 0;
s.f9 = 0;
s.f10 = 0;
s.f11 = 0;
s.f12 = 0;
s.f13 = 0;
s.f14 = 0;
s.f15 = 0;
s.f16 = 0;
s.f17 = 0;
s.f18 = 0;
s.f19 = 0;
s.f20 = 0;
s.f21 = 0;
s.f22 = 0;
s.f23 = 0;
s.f24 = 0;
}