FreeChainXenon/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

configure.tgt (target_cpu): Handle sparc and sparc64 & sparcv9.

Browse source 
* configure.tgt (target_cpu): Handle sparc and sparc64 & sparcv9.
	* config/sparc/cacheline.h: New file.
	* config/sparc/target.h: Likewise.
	* config/sparc/sjlj.S: Likewise.
	* config/linux/sparc/futex_bits.h: Likewise.

From-SVN: r184177
This commit is contained in:
Eric Botcazou 2012-02-13 21:51:44 +00:00 • committed by Eric Botcazou
parent 255a9a1bb5
commit f3f5e3c32e
6 changed files with 282 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
libitm/ChangeLog
View file

@ -1,4 +1,12 @@
2012-02-11 Eric Botcazou <ebotcazou@adacore.com>
2012-02-13 Eric Botcazou <ebotcazou@adacore.com>
* configure.tgt (target_cpu): Handle sparc and sparc64 & sparcv9.
* config/sparc/cacheline.h: New file.
* config/sparc/target.h: Likewise.
* config/sparc/sjlj.S: Likewise.
* config/linux/sparc/futex_bits.h: Likewise.
2012-02-13 Eric Botcazou <ebotcazou@adacore.com>
* configure.ac (link_itm): Fix comment.
* configure: Regenerate.

62
libitm/config/linux/sparc/futex_bits.h Normal file
View file

@ -0,0 +1,62 @@
/* Copyright (C) 2012 Free Software Foundation, Inc.
This file is part of the GNU Transactional Memory Library (libitm).
Libitm is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include <sys/syscall.h>
static inline long
sys_futex0 (std::atomic<int> *addr, int op, int val)
{
register long int g1 __asm__ ("g1");
register long int o0 __asm__ ("o0");
register long int o1 __asm__ ("o1");
register long int o2 __asm__ ("o2");
register long int o3 __asm__ ("o3");
long res;
g1 = SYS_futex;
o0 = (long) addr;
o1 = op;
o2 = val;
o3 = 0;
#ifdef __arch64__
__asm volatile ("ta 0x6d"
#else
__asm volatile ("ta 0x10"
#endif
: "=r"(g1), "=r"(o0)
: "0"(g1), "1"(o0), "r"(o1), "r"(o2), "r"(o3)
: "g2", "g3", "g4", "g5", "g6",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
"f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
"f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
"cc", "memory");
res = o0;
if (__builtin_expect ((unsigned long) res >= -515UL, 0))
res =- res;
return res;
}

41
libitm/config/sparc/cacheline.h Normal file
View file

@ -0,0 +1,41 @@
/* Copyright (C) 2012 Free Software Foundation, Inc.
This file is part of the GNU Transactional Memory Library (libitm).
Libitm is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef LIBITM_SPARC_CACHELINE_H
#define LIBITM_SPARC_CACHELINE_H 1
// A cacheline is the smallest unit with which locks are associated.
// The current implementation of the _ITM_[RW] barriers assumes that
// all data types can fit (aligned) within a cachline, which means
// in practice sizeof(complex long double) is the smallest cacheline size.
// It ought to be small enough for efficient manipulation of the
// modification mask, below.
#ifdef __arch64__
# define CACHELINE_SIZE 64
#else
# define CACHELINE_SIZE 32
#endif
#include "config/generic/cacheline.h"
#endif // LIBITM_SPARC_CACHELINE_H

96
libitm/config/sparc/sjlj.S Normal file
View file

@ -0,0 +1,96 @@
/* Copyright (C) 2012 Free Software Foundation, Inc.
This file is part of the GNU Transactional Memory Library (libitm).
Libitm is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "asmcfi.h"
#ifdef __arch64__
# define WORD_SIZE 8
# define MIN_FRAME_SIZE 176
# define STACK_BIAS 2047
# define load ldx
# define store stx
#else
# define WORD_SIZE 4
# define MIN_FRAME_SIZE 96
# define STACK_BIAS 0
# define load ld
# define store st
#endif
/* Fields of the JmpBuf structure. */
#define JB_CFA 0
#define JB_PC 1
#define OFFSET(FIELD) ((FIELD) * WORD_SIZE)
/* The frame size must be a multiple of the double-word size. */
#define FRAME_SIZE (MIN_FRAME_SIZE + 2 * WORD_SIZE)
#define JB_OFFSET (STACK_BIAS + MIN_FRAME_SIZE)
.text
.align 4
.globl _ITM_beginTransaction
.type _ITM_beginTransaction, #function
.proc 016
_ITM_beginTransaction:
cfi_startproc
add %sp, STACK_BIAS, %g1
sub %sp, FRAME_SIZE, %sp
cfi_def_cfa_offset(STACK_BIAS + FRAME_SIZE)
store %g1, [%sp + JB_OFFSET + OFFSET (JB_CFA)]
store %o7, [%sp + JB_OFFSET + OFFSET (JB_PC)]
/* ??? This triggers an internal error in GDB. */
cfi_offset(%o7, -WORD_SIZE)
call GTM_begin_transaction
add %sp, JB_OFFSET, %o1
load [%sp + JB_OFFSET + OFFSET (JB_PC)], %o7
jmp %o7+8
add %sp, FRAME_SIZE, %sp
cfi_def_cfa_offset(STACK_BIAS)
cfi_endproc
.size _ITM_beginTransaction, . - _ITM_beginTransaction
.align 4
.globl GTM_longjmp
#ifdef HAVE_ATTRIBUTE_VISIBILITY
.hidden GTM_longjmp
#endif
.type GTM_longjmp, #function
.proc 016
GTM_longjmp:
cfi_startproc
flushw
load [%o1 + OFFSET (JB_CFA)], %fp
cfi_def_cfa(%fp, 0)
#if STACK_BIAS
sub %fp, STACK_BIAS, %fp
cfi_def_cfa_offset(STACK_BIAS)
#endif
load [%o1 + OFFSET (JB_PC)], %o7
jmp %o7+8
restore %g0, %o0, %o0
cfi_endproc
.size GTM_longjmp, . - GTM_longjmp
#ifdef __linux__
.section .note.GNU-stack, "", @progbits
#endif

46
libitm/config/sparc/target.h Normal file
View file

@ -0,0 +1,46 @@
/* Copyright (C) 2012 Free Software Foundation, Inc.
This file is part of the GNU Transactional Memory Library (libitm).
Libitm is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
namespace GTM HIDDEN {
typedef struct gtm_jmpbuf
{
void *cfa;
unsigned long pc;
} gtm_jmpbuf;
/* UltraSPARC processors generally use a fixed page size of 8K. */
#define PAGE_SIZE 8192
#define FIXED_PAGE_SIZE 1
/* The size of one line in hardware caches (in bytes). We use the primary
cache line size documented for the UltraSPARC T1/T2. */
#define HW_CACHELINE_SIZE 16
static inline void
cpu_relax (void)
{
__asm volatile ("" : : : "memory");
}
} // namespace GTM

28
libitm/configure.tgt
View file

@ -66,6 +66,34 @@ case "${target_cpu}" in
sh*) ARCH=sh ;;
sparc)
case " ${CC} ${CFLAGS} " in
*" -m64 "*)
;;
*)
if test -z "$with_cpu"; then
XCFLAGS="${XCFLAGS} -mcpu=v9"
fi
esac
ARCH=sparc
;;
sparc64|sparcv9)
case " ${CC} ${CFLAGS} " in
*" -m32 "*)
XCFLAGS="${XCFLAGS} -mcpu=v9"
;;
*" -m64 "*)
;;
*)
if test "x$with_cpu" = xv8; then
XCFLAGS="${XCFLAGS} -mcpu=v9"
fi
;;
esac
ARCH=sparc
;;
x86_64)
case " ${CC} ${CFLAGS} " in
*" -m32 "*)