mips-ps-3d.md (scc_ps, s<code>_ps): New patterns.
2006-05-06 Chao-ying Fu <fu@mips.com> Richard Sandiford <richard@codesourcery.com> gcc/ * config/mips/mips-ps-3d.md (scc_ps, s<code>_ps): New patterns. (vcondv2sf, sminv2sf3, smaxv2sf3): Likewise. * config/mips/mips.md (UNSPEC_SCC): New constant. * config/mips/mips-protos.h (mips_expand_vcondv2sf): Declare. * config/mips/mips.c (mips_reverse_fp_cond_p): New function. (mips_emit_compare): Use it. (mips_expand_vcondv2sf): New function. gcc/testsuite/ * gcc.target/mips/mips-ps-5.c: New file. From-SVN: r113644
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Richard Sandiford
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7 changed files with 143 additions and 14 deletions
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@ -1,3 +1,14 @@
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2006-05-08 Chao-ying Fu <fu@mips.com>
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Richard Sandiford <richard@codesourcery.com>
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* config/mips/mips-ps-3d.md (scc_ps, s<code>_ps): New patterns.
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(vcondv2sf, sminv2sf3, smaxv2sf3): Likewise.
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* config/mips/mips.md (UNSPEC_SCC): New constant.
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* config/mips/mips-protos.h (mips_expand_vcondv2sf): Declare.
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* config/mips/mips.c (mips_reverse_fp_cond_p): New function.
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(mips_emit_compare): Use it.
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(mips_expand_vcondv2sf): New function.
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2006-05-08 Daniel Berlin <dberlin@dberlin.org>
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Fix PR tree-optimization/27093
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@ -168,6 +168,7 @@ extern void mips_restore_gp (void);
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#ifdef RTX_CODE
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extern bool mips_emit_scc (enum rtx_code, rtx);
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extern void gen_conditional_branch (rtx *, enum rtx_code);
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extern void mips_expand_vcondv2sf (rtx, rtx, rtx, enum rtx_code, rtx, rtx);
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#endif
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extern void gen_conditional_move (rtx *);
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extern void mips_gen_conditional_trap (rtx *);
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@ -381,6 +381,32 @@
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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;; An expander for generating an scc operation.
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(define_expand "scc_ps"
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[(set (match_operand:CCV2 0)
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(unspec:CCV2 [(match_operand 1)] UNSPEC_SCC))])
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(define_insn "s<code>_ps"
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[(set (match_operand:CCV2 0 "register_operand" "=z")
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(unspec:CCV2
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[(fcond (match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f"))]
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UNSPEC_SCC))]
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"TARGET_PAIRED_SINGLE_FLOAT"
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"c.<fcond>.ps\t%0,%1,%2"
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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(define_insn "s<code>_ps"
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[(set (match_operand:CCV2 0 "register_operand" "=z")
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(unspec:CCV2
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[(swapped_fcond (match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f"))]
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UNSPEC_SCC))]
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"TARGET_PAIRED_SINGLE_FLOAT"
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"c.<swapped_fcond>.ps\t%0,%2,%1"
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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;----------------------------------------------------------------------------
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; Floating Point Branch Instructions.
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@ -528,3 +554,40 @@
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"recip2.<fmt>\t%0,%1,%2"
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[(set_attr "type" "frdiv2")
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(set_attr "mode" "<UNITMODE>")])
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(define_expand "vcondv2sf"
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[(set (match_operand:V2SF 0 "register_operand")
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(if_then_else:V2SF
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(match_operator 3 ""
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[(match_operand:V2SF 4 "register_operand")
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(match_operand:V2SF 5 "register_operand")])
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(match_operand:V2SF 1 "register_operand")
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(match_operand:V2SF 2 "register_operand")))]
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"TARGET_PAIRED_SINGLE_FLOAT"
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{
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mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
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GET_CODE (operands[3]), operands[4], operands[5]);
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DONE;
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})
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(define_expand "sminv2sf3"
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[(set (match_operand:V2SF 0 "register_operand")
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(smin:V2SF (match_operand:V2SF 1 "register_operand")
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(match_operand:V2SF 2 "register_operand")))]
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"TARGET_PAIRED_SINGLE_FLOAT"
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{
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mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
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LE, operands[1], operands[2]);
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DONE;
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})
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(define_expand "smaxv2sf3"
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[(set (match_operand:V2SF 0 "register_operand")
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(smax:V2SF (match_operand:V2SF 1 "register_operand")
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(match_operand:V2SF 2 "register_operand")))]
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"TARGET_PAIRED_SINGLE_FLOAT"
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{
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mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
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LE, operands[2], operands[1]);
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DONE;
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})
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@ -3116,6 +3116,27 @@ mips_zero_if_equal (rtx cmp0, rtx cmp1)
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cmp0, cmp1, 0, 0, OPTAB_DIRECT);
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}
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/* Convert *CODE into a code that can be used in a floating-point
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scc instruction (c.<cond>.<fmt>). Return true if the values of
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the condition code registers will be inverted, with 0 indicating
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that the condition holds. */
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static bool
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mips_reverse_fp_cond_p (enum rtx_code *code)
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{
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switch (*code)
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{
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case NE:
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case LTGT:
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case ORDERED:
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*code = reverse_condition_maybe_unordered (*code);
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return true;
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default:
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return false;
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}
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}
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/* Convert a comparison into something that can be used in a branch or
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conditional move. cmp_operands[0] and cmp_operands[1] are the values
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being compared and *CODE is the code used to compare them.
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@ -3173,20 +3194,8 @@ mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
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Set CMP_CODE to the code of the comparison instruction and
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*CODE to the code that the branch or move should use. */
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switch (*code)
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{
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case NE:
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case LTGT:
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case ORDERED:
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cmp_code = reverse_condition_maybe_unordered (*code);
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*code = EQ;
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break;
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default:
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cmp_code = *code;
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*code = NE;
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break;
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}
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*code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
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*op0 = (ISA_HAS_8CC
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? gen_reg_rtx (CCmode)
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: gen_rtx_REG (CCmode, FPSW_REGNUM));
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@ -3232,6 +3241,30 @@ gen_conditional_branch (rtx *operands, enum rtx_code code)
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emit_jump_insn (gen_condjump (condition, operands[0]));
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}
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/* Implement:
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(set temp (COND:CCV2 CMP_OP0 CMP_OP1))
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(set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
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void
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mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
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enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
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{
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rtx cmp_result;
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bool reversed_p;
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reversed_p = mips_reverse_fp_cond_p (&cond);
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cmp_result = gen_reg_rtx (CCV2mode);
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emit_insn (gen_scc_ps (cmp_result,
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gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
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if (reversed_p)
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emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
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cmp_result));
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else
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emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
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cmp_result));
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}
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/* Emit the common code for conditional moves. OPERANDS is the array
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of operands passed to the conditional move define_expand. */
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@ -73,6 +73,7 @@
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(UNSPEC_RECIP1 210)
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(UNSPEC_RECIP2 211)
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(UNSPEC_SINGLE_CC 212)
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(UNSPEC_SCC 213)
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;; MIPS DSP ASE Revision 0.98 3/24/2005
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(UNSPEC_ADDQ 300)
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@ -1,3 +1,7 @@
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2006-05-06 Richard Sandiford <richard@codesourcery.com>
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* gcc.target/mips/mips-ps-5.c: New file.
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2006-05-08 Jan Hubicka <jh@suse.cz>
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PR middle-end/25962
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16
gcc/testsuite/gcc.target/mips/mips-ps-5.c
Normal file
16
gcc/testsuite/gcc.target/mips/mips-ps-5.c
Normal file
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@ -0,0 +1,16 @@
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/* { dg-do compile } */
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/* { dg-mips-options "-mips64 -O2 -mpaired-single -mhard-float -mgp64 -ftree-vectorize" } */
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extern float a[], b[], c[];
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void
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foo (void)
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{
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int i;
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for (i = 0; i < 16; i++)
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a[i] = b[i] == c[i] + 1 ? b[i] : c[i];
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}
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/* { dg-final { scan-assembler "add\\.ps" } } */
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/* { dg-final { scan-assembler "c\\.eq\\.ps" } } */
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/* { dg-final { scan-assembler "mov\[tf\]\\.ps" } } */
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