mips-ps-3d.md (scc_ps, s<code>_ps): New patterns.

2006-05-06  Chao-ying Fu  <fu@mips.com>
	    Richard Sandiford  <richard@codesourcery.com>

gcc/
	* config/mips/mips-ps-3d.md (scc_ps, s<code>_ps): New patterns.
	(vcondv2sf, sminv2sf3, smaxv2sf3): Likewise.
	* config/mips/mips.md (UNSPEC_SCC): New constant.
	* config/mips/mips-protos.h (mips_expand_vcondv2sf): Declare.
	* config/mips/mips.c (mips_reverse_fp_cond_p): New function.
	(mips_emit_compare): Use it.
	(mips_expand_vcondv2sf): New function.

gcc/testsuite/
	* gcc.target/mips/mips-ps-5.c: New file.

From-SVN: r113644

gcc/ChangeLog

@@ -1,3 +1,14 @@
+2006-05-08  Chao-ying Fu  <fu@mips.com>
+	    Richard Sandiford  <richard@codesourcery.com>
+
+	* config/mips/mips-ps-3d.md (scc_ps, s<code>_ps): New patterns.
+	(vcondv2sf, sminv2sf3, smaxv2sf3): Likewise.
+	* config/mips/mips.md (UNSPEC_SCC): New constant.
+	* config/mips/mips-protos.h (mips_expand_vcondv2sf): Declare.
+	* config/mips/mips.c (mips_reverse_fp_cond_p): New function.
+	(mips_emit_compare): Use it.
+	(mips_expand_vcondv2sf): New function.
+
 2006-05-08  Daniel Berlin  <dberlin@dberlin.org>
 
 	Fix PR tree-optimization/27093

gcc/config/mips/mips-protos.h

@@ -168,6 +168,7 @@ extern void mips_restore_gp (void);
 #ifdef RTX_CODE
 extern bool mips_emit_scc (enum rtx_code, rtx);
 extern void gen_conditional_branch (rtx *, enum rtx_code);
+extern void mips_expand_vcondv2sf (rtx, rtx, rtx, enum rtx_code, rtx, rtx);
 #endif
 extern void gen_conditional_move (rtx *);
 extern void mips_gen_conditional_trap (rtx *);

gcc/config/mips/mips-ps-3d.md

@@ -381,6 +381,32 @@
   [(set_attr "type" "fcmp")
    (set_attr "mode" "FPSW")])
 
+;; An expander for generating an scc operation.
+(define_expand "scc_ps"
+  [(set (match_operand:CCV2 0)
+	(unspec:CCV2 [(match_operand 1)] UNSPEC_SCC))])
+
+(define_insn "s<code>_ps"
+  [(set (match_operand:CCV2 0 "register_operand" "=z")
+	(unspec:CCV2
+	   [(fcond (match_operand:V2SF 1 "register_operand" "f")
+		   (match_operand:V2SF 2 "register_operand" "f"))]
+	   UNSPEC_SCC))]
+  "TARGET_PAIRED_SINGLE_FLOAT"
+  "c.<fcond>.ps\t%0,%1,%2"
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "FPSW")])
+
+(define_insn "s<code>_ps"
+  [(set (match_operand:CCV2 0 "register_operand" "=z")
+	(unspec:CCV2
+	   [(swapped_fcond (match_operand:V2SF 1 "register_operand" "f")
+			   (match_operand:V2SF 2 "register_operand" "f"))]
+	   UNSPEC_SCC))]
+  "TARGET_PAIRED_SINGLE_FLOAT"
+  "c.<swapped_fcond>.ps\t%0,%2,%1"
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "FPSW")])
 
 ;----------------------------------------------------------------------------
 ; Floating Point Branch Instructions.
@@ -528,3 +554,40 @@
   "recip2.<fmt>\t%0,%1,%2"
   [(set_attr "type" "frdiv2")
    (set_attr "mode" "<UNITMODE>")])
+
+(define_expand "vcondv2sf"
+  [(set (match_operand:V2SF 0 "register_operand")
+	(if_then_else:V2SF
+	  (match_operator 3 ""
+	    [(match_operand:V2SF 4 "register_operand")
+	     (match_operand:V2SF 5 "register_operand")])
+	  (match_operand:V2SF 1 "register_operand")
+	  (match_operand:V2SF 2 "register_operand")))]
+  "TARGET_PAIRED_SINGLE_FLOAT"
+{
+  mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
+			 GET_CODE (operands[3]), operands[4], operands[5]);
+  DONE;
+})
+
+(define_expand "sminv2sf3"
+  [(set (match_operand:V2SF 0 "register_operand")
+	(smin:V2SF (match_operand:V2SF 1 "register_operand")
+		   (match_operand:V2SF 2 "register_operand")))]
+  "TARGET_PAIRED_SINGLE_FLOAT"
+{
+  mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
+			 LE, operands[1], operands[2]);
+  DONE;
+})
+
+(define_expand "smaxv2sf3"
+  [(set (match_operand:V2SF 0 "register_operand")
+	(smax:V2SF (match_operand:V2SF 1 "register_operand")
+		   (match_operand:V2SF 2 "register_operand")))]
+  "TARGET_PAIRED_SINGLE_FLOAT"
+{
+  mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
+			 LE, operands[2], operands[1]);
+  DONE;
+})

gcc/config/mips/mips.c

@@ -3116,6 +3116,27 @@ mips_zero_if_equal (rtx cmp0, rtx cmp1)
 		       cmp0, cmp1, 0, 0, OPTAB_DIRECT);
 }
 
+/* Convert *CODE into a code that can be used in a floating-point
+   scc instruction (c.<cond>.<fmt>).  Return true if the values of
+   the condition code registers will be inverted, with 0 indicating
+   that the condition holds.  */
+
+static bool
+mips_reverse_fp_cond_p (enum rtx_code *code)
+{
+  switch (*code)
+    {
+    case NE:
+    case LTGT:
+    case ORDERED:
+      *code = reverse_condition_maybe_unordered (*code);
+      return true;
+
+    default:
+      return false;
+    }
+}
+
 /* Convert a comparison into something that can be used in a branch or
    conditional move.  cmp_operands[0] and cmp_operands[1] are the values
    being compared and *CODE is the code used to compare them.
@@ -3173,20 +3194,8 @@ mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
 
 	 Set CMP_CODE to the code of the comparison instruction and
 	 *CODE to the code that the branch or move should use.  */
-      switch (*code)
+      cmp_code = *code;
-	{
+      *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
-	case NE:
-	case LTGT:
-	case ORDERED:
-	  cmp_code = reverse_condition_maybe_unordered (*code);
-	  *code = EQ;
-	  break;
-
-	default:
-	  cmp_code = *code;
-	  *code = NE;
-	  break;
-	}
       *op0 = (ISA_HAS_8CC
 	      ? gen_reg_rtx (CCmode)
 	      : gen_rtx_REG (CCmode, FPSW_REGNUM));
@@ -3232,6 +3241,30 @@ gen_conditional_branch (rtx *operands, enum rtx_code code)
   emit_jump_insn (gen_condjump (condition, operands[0]));
 }
 
+/* Implement:
+
+   (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
+   (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS))  */
+
+void
+mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
+		       enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
+{
+  rtx cmp_result;
+  bool reversed_p;
+
+  reversed_p = mips_reverse_fp_cond_p (&cond);
+  cmp_result = gen_reg_rtx (CCV2mode);
+  emit_insn (gen_scc_ps (cmp_result,
+			 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
+  if (reversed_p)
+    emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
+					 cmp_result));
+  else
+    emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
+					 cmp_result));
+}
+
 /* Emit the common code for conditional moves.  OPERANDS is the array
    of operands passed to the conditional move define_expand.  */
 

gcc/config/mips/mips.md

@@ -73,6 +73,7 @@
    (UNSPEC_RECIP1		210)
    (UNSPEC_RECIP2		211)
    (UNSPEC_SINGLE_CC		212)
+   (UNSPEC_SCC			213)
 
    ;; MIPS DSP ASE Revision 0.98 3/24/2005
    (UNSPEC_ADDQ			300)

gcc/testsuite/ChangeLog

@@ -1,3 +1,7 @@
+2006-05-06  Richard Sandiford  <richard@codesourcery.com>
+
+	* gcc.target/mips/mips-ps-5.c: New file.
+
 2006-05-08  Jan Hubicka  <jh@suse.cz>
 
 	PR middle-end/25962

gcc/testsuite/gcc.target/mips/mips-ps-5.c

@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-mips64 -O2 -mpaired-single -mhard-float -mgp64 -ftree-vectorize" } */
+
+extern float a[], b[], c[];
+
+void
+foo (void)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = b[i] == c[i] + 1 ? b[i] : c[i];
+}
+
+/* { dg-final { scan-assembler "add\\.ps" } } */
+/* { dg-final { scan-assembler "c\\.eq\\.ps" } } */
+/* { dg-final { scan-assembler "mov\[tf\]\\.ps" } } */