RISC-V: Enable ztso tests on rv32

This patch transitions the ztso testcases to use the testsuite infrastructure,
enabling the tests on both rv64 and rv32 targets.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso extension to
	dg-options for dg-do compile.
	* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-fence-1.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-fence-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-fence-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-fence-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-fence-5.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-load-1.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-load-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-load-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-store-1.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-store-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-store-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
	* lib/target-supports.exp: Add testing infrastructure to require the
	Ztso extension or add it to an existing -march.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-1.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that fence mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-2.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that fence mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-3.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that fence mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-4.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that fence mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-5.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that fence mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-1.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that load mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-2.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that load mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-3.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that load mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-1.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that store mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-2.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that store mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-3.c

@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that store mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

gcc/testsuite/lib/target-supports.exp

@@ -1961,6 +1961,17 @@ proc check_effective_target_riscv_zfh { } {
     }]
 }
 
+# Return 1 if the target arch supports the TSO memory ordering extension,
+# 0 otherwise. Cache the result.
+
+proc check_effective_target_riscv_ztso { } {
+    return [check_no_compiler_messages riscv_ext_ztso assembly {
+       #ifndef __riscv_ztso
+       #error "Not __riscv_ztso"
+       #endif
+    }]
+}
+
 # Return 1 if we can execute code when using dg-add-options riscv_v
 
 proc check_effective_target_riscv_v_ok { } {
@@ -2040,7 +2051,7 @@ proc check_effective_target_riscv_zvfh_ok { } {
 proc riscv_get_arch { } {
     set gcc_march ""
     # ??? do we neeed to add more extensions to the list below?
-    foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh } {
+    foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh ztso } {
 	if { [check_no_compiler_messages  riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] {
 		#ifndef DEF
 		#error "Not DEF"
@@ -2111,6 +2122,18 @@ proc add_options_for_riscv_zfh { flags } {
     return "$flags -march=[riscv_get_arch]_zfh"
 }
 
+proc add_options_for_riscv_ztso { flags } {
+    if { [lsearch $flags -march=*] >= 0 } {
+	# If there are multiple -march flags, we have to adjust all of them.
+	set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_ztso ]
+	return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_ztso[[:alnum:]_.]*)_ztso} $flags \\1 ]
+    }
+    if { [check_effective_target_riscv_ztso] } {
+	return "$flags"
+    }
+    return "$flags -march=[riscv_get_arch]_ztso"
+}
+
 proc add_options_for_riscv_zvfh { flags } {
     if { [lsearch $flags -march=*] >= 0 } {
 	# If there are multiple -march flags, we have to adjust all of them.