rs6000.md (f32_vsx): New mode attributes to refine the constraints used on 32/64-bit floating point...
2014-09-23 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.md (f32_vsx): New mode attributes to refine the constraints used on 32/64-bit floating point moves. (f32_av): Likewise. (f64_vsx): Likewise. (f64_dm): Likewise. (f64_av): Likewise. (BOOL_REGS_OUTPUT): Use wt constraint for TImode instead of wa. (BOOL_REGS_OP1): Likewise. (BOOL_REGS_OP2): Likewise. (BOOL_REGS_UNARY): Likewise. (mov<mode>_hardfloat, SFmode/SDmode): Tighten down constraints for 32/64-bit floating point moves. Do not use wa, instead use ww/ws for moves involving VSX registers. Do not use constraints that target VSX registers for decimal types. (mov<mode>_hardfloat32, DFmode/DDmode): Likewise. (mov<mode>_hardfloat64, DFmode/DDmode): Likewise. From-SVN: r215521
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Michael Meissner
Michael Meissner
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commit
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2 changed files with 46 additions and 10 deletions
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@ -1,3 +1,22 @@
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2014-09-23 Michael Meissner <meissner@linux.vnet.ibm.com>
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* config/rs6000/rs6000.md (f32_vsx): New mode attributes to
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refine the constraints used on 32/64-bit floating point moves.
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(f32_av): Likewise.
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(f64_vsx): Likewise.
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(f64_dm): Likewise.
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(f64_av): Likewise.
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(BOOL_REGS_OUTPUT): Use wt constraint for TImode instead of wa.
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(BOOL_REGS_OP1): Likewise.
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(BOOL_REGS_OP2): Likewise.
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(BOOL_REGS_UNARY): Likewise.
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(mov<mode>_hardfloat, SFmode/SDmode): Tighten down constraints for
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32/64-bit floating point moves. Do not use wa, instead use ww/ws
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for moves involving VSX registers. Do not use constraints that
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target VSX registers for decimal types.
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(mov<mode>_hardfloat32, DFmode/DDmode): Likewise.
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(mov<mode>_hardfloat64, DFmode/DDmode): Likewise.
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2014-09-23 Jan Hubicka <hubicka@ucw.cz>
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* tree.h (int_bit_position): Turn into inline function;
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@ -401,8 +401,25 @@
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(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
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; Definitions for 32-bit fpr direct move
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; At present, the decimal modes are not allowed in the traditional altivec
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; registers, so restrict the constraints to just the traditional FPRs.
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(define_mode_attr f32_dm [(SF "wn") (SD "wh")])
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; Definitions for 32-bit VSX
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(define_mode_attr f32_vsx [(SF "ww") (SD "wn")])
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; Definitions for 32-bit use of altivec registers
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(define_mode_attr f32_av [(SF "wu") (SD "wn")])
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; Definitions for 64-bit VSX
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(define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
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; Definitions for 64-bit direct move
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(define_mode_attr f64_dm [(DF "wk") (DD "wh")])
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; Definitions for 64-bit use of altivec registers
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(define_mode_attr f64_av [(DF "wv") (DD "wn")])
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; These modes do not fit in integer registers in 32-bit mode.
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; but on e500v2, the gpr are 64 bit registers
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(define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
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@ -528,7 +545,7 @@
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;; either.
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;; Mode attribute for boolean operation register constraints for output
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(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
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(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v")
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(PTI "&r,r,r")
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(V16QI "wa,v,&?r,?r,?r")
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(V8HI "wa,v,&?r,?r,?r")
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@ -539,7 +556,7 @@
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(V1TI "wa,v,&?r,?r,?r")])
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;; Mode attribute for boolean operation register constraints for operand1
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(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
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(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v")
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(PTI "r,0,r")
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(V16QI "wa,v,r,0,r")
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(V8HI "wa,v,r,0,r")
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@ -550,7 +567,7 @@
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(V1TI "wa,v,r,0,r")])
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;; Mode attribute for boolean operation register constraints for operand2
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(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
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(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v")
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(PTI "r,r,0")
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(V16QI "wa,v,r,r,0")
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(V8HI "wa,v,r,r,0")
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@ -563,7 +580,7 @@
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;; Mode attribute for boolean operation register constraints for operand1
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;; for one_cmpl. To simplify things, we repeat the constraint where 0
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;; is used for operand1 or operand2
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(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
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(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v")
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(PTI "r,0,0")
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(V16QI "wa,v,r,0,0")
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(V8HI "wa,v,r,0,0")
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@ -7805,8 +7822,8 @@
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}")
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(define_insn "mov<mode>_hardfloat"
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[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
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(match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
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[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
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(match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r, h, 0, G,Fn"))]
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"(gpc_reg_operand (operands[0], <MODE>mode)
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|| gpc_reg_operand (operands[1], <MODE>mode))
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&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
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@ -7944,8 +7961,8 @@
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;; reloading.
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(define_insn "*mov<mode>_hardfloat32"
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))]
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"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
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&& (gpc_reg_operand (operands[0], <MODE>mode)
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|| gpc_reg_operand (operands[1], <MODE>mode))"
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@ -7982,8 +7999,8 @@
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; ld/std require word-aligned displacements -> 'Y' constraint.
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; List Y->r and r->Y before r->r for reload.
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(define_insn "*mov<mode>_hardfloat64"
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))]
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))]
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
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&& (gpc_reg_operand (operands[0], <MODE>mode)
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|| gpc_reg_operand (operands[1], <MODE>mode))"
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