re PR rtl-optimization/50396 (SSE division by zero generates incorrect code with optimizations enabled)
2011-12-23 Richard Guenther <rguenther@suse.de> PR rtl-optimization/50396 * simplify-rtx.c (simplify_binary_operation_1): Properly guard code that only works for integers. * gcc.dg/torture/pr50396.c: New testcase. From-SVN: r182653
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2011-12-23 Richard Guenther <rguenther@suse.de>
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PR rtl-optimization/50396
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* simplify-rtx.c (simplify_binary_operation_1): Properly
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guard code that only works for integers.
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2011-12-23 Tristan Gingold <gingold@adacore.com>
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* config/vms/vms-crtlmap.map (log10): Fix typo.
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@ -2953,7 +2953,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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}
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}
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}
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else
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else if (SCALAR_INT_MODE_P (mode))
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{
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/* 0/x is 0 (or x&0 if x has side-effects). */
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if (trueop0 == CONST0_RTX (mode)
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2011-12-23 Richard Guenther <rguenther@suse.de>
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PR rtl-optimization/50396
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* gcc.dg/torture/pr50396.c: New testcase.
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2011-12-22 Bin Cheng <bin.cheng@arm.com>
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PR tree-optimization/43491
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21
gcc/testsuite/gcc.dg/torture/pr50396.c
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21
gcc/testsuite/gcc.dg/torture/pr50396.c
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/* { dg-do run } */
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extern void abort (void);
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typedef float vf128 __attribute__((vector_size(16)));
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typedef float vf64 __attribute__((vector_size(8)));
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int main()
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{
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#if !__FINITE_MATH_ONLY__
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#if __FLT_HAS_QUIET_NAN__
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vf128 v = (vf128){ 0.f, 0.f, 0.f, 0.f };
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vf64 u = (vf64){ 0.f, 0.f };
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v = v / (vf128){ 0.f, 0.f, 0.f, 0.f };
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if (v[0] == v[0])
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abort ();
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u = u / (vf64){ 0.f, 0.f };
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if (u[0] == u[0])
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abort ();
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#endif
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#endif
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return 0;
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}
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