[ARM] Add support for -mpure-code in thumb-1 (v6m)
This patch extends support for -mpure-code to all thumb-1 processors,
by removing the need for MOVT.
Symbol addresses are built using upper8_15, upper0_7, lower8_15 and
lower0_7 relocations, and constants are built using sequences of
movs/adds and lsls instructions.
The extension of the *thumb1_movhf pattern uses always the same size
(6) although it can emit a shorter sequence when possible. This is
similar to what *arm32_movhf already does.
CASE_VECTOR_PC_RELATIVE is now false with -mpure-code, to avoid
generating invalid assembly code with differences from symbols from
two different sections (the difference cannot be computed by the
assembler).
Tests pr45701-[12].c needed a small adjustment to avoid matching
upper8_15 when looking for the r8 register.
Test no-literal-pool.c is augmented with __fp16, so it now uses
-mfp16-format=ieee.
Test thumb1-Os-mult.c generates an inline code sequence with
-mpure-code and computes the multiplication by using a sequence of
add/shift rather than using the multiply instruction, so we skip it in
presence of -mpure-code.
With -mcpu=cortex-m0, the pure-code/no-literal-pool.c fails because
code like:
static char *p = "Hello World";
char *
testchar ()
{
return p + 4;
}
generates 2 indirections (I removed non-essential directives/code)
.section .rodata
.LC0:
.ascii "Hello World\000"
.data
p:
.word .LC0
.section .rodata
.LC2:
.word p
.section .text,"0x20000006",%progbits
testchar:
push {r7, lr}
add r7, sp, #0
movs r3, #:upper8_15:#.LC2
lsls r3, #8
adds r3, #:upper0_7:#.LC2
lsls r3, #8
adds r3, #:lower8_15:#.LC2
lsls r3, #8
adds r3, #:lower0_7:#.LC2
ldr r3, [r3]
ldr r3, [r3]
adds r3, r3, #4
movs r0, r3
mov sp, r7
@ sp needed
pop {r7, pc}
By contrast, when using -mcpu=cortex-m4, the code looks like:
.section .rodata
.LC0:
.ascii "Hello World\000"
.data
p:
.word .LC0
testchar:
push {r7}
add r7, sp, #0
movw r3, #:lower16:p
movt r3, #:upper16:p
ldr r3, [r3]
adds r3, r3, #4
mov r0, r3
mov sp, r7
pop {r7}
bx lr
I haven't found yet how to make code for cortex-m0 apply upper/lower
relocations to "p" instead of .LC2. The current code looks functional,
but could be improved.
2019-10-18 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* config/arm/arm-protos.h (thumb1_gen_const_int): Add new prototype.
* config/arm/arm.c (arm_option_check_internal): Remove restriction
on MOVT for -mpure-code.
(thumb1_gen_const_int): New function.
(thumb1_legitimate_address_p): Support -mpure-code.
(thumb1_rtx_costs): Likewise.
(thumb1_size_rtx_costs): Likewise.
(arm_thumb1_mi_thunk): Likewise.
* config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Likewise.
* config/arm/thumb1.md (thumb1_movsi_symbol_ref): New.
(*thumb1_movhf): Support -mpure-code.
gcc/testsuite/
* gcc.target/arm/pr45701-1.c: Adjust for -mpure-code.
* gcc.target/arm/pr45701-2.c: Likewise.
* gcc.target/arm/pure-code/no-literal-pool.c: Add tests for
__fp16.
* gcc.target/arm/pure-code/pure-code.exp: Remove thumb2 and movt
conditions.
* gcc.target/arm/thumb1-Os-mult.c: Skip if -mpure-code is used.
From-SVN: r279463
This commit is contained in:
Christophe Lyon
Christophe Lyon
parent
6226f5925f
commit
e24f6408df
12 changed files with 192 additions and 30 deletions
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@ -1,3 +1,18 @@
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2019-12-17 Christophe Lyon <christophe.lyon@linaro.org>
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* config/arm/arm-protos.h (thumb1_gen_const_int): Add new prototype.
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* config/arm/arm.c (arm_option_check_internal): Remove restriction
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on MOVT for -mpure-code.
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(thumb1_gen_const_int): New function.
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(thumb1_legitimate_address_p): Support -mpure-code.
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(thumb1_rtx_costs): Likewise.
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(thumb1_size_rtx_costs): Likewise.
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(arm_thumb1_mi_thunk): Likewise.
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* config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Likewise.
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* config/arm/thumb1.md (thumb1_movsi_symbol_ref): New.
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(*thumb1_movhf): Support -mpure-code.
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* doc/invoke.texi (-mpure-code): Remove restriction on MOVT.
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2019-12-17 Andrew Stubbs <ams@codesourcery.com>
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* tree-vect-loop.c (vect_create_epilog_for_reduction): Mention pr92772
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@ -71,6 +71,7 @@ extern bool arm_small_register_classes_for_mode_p (machine_mode);
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extern int const_ok_for_arm (HOST_WIDE_INT);
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extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
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extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
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extern void thumb1_gen_const_int (rtx, HOST_WIDE_INT);
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extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
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HOST_WIDE_INT, rtx, rtx, int);
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extern int legitimate_pic_operand_p (rtx);
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@ -2893,13 +2893,18 @@ arm_option_check_internal (struct gcc_options *opts)
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{
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const char *flag = (target_pure_code ? "-mpure-code" :
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"-mslow-flash-data");
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bool common_unsupported_modes = arm_arch_notm || flag_pic || TARGET_NEON;
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/* We only support -mpure-code and -mslow-flash-data on M-profile targets
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with MOVT. */
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if (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON)
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/* We only support -mslow-flash-data on M-profile targets with
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MOVT. */
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if (target_slow_flash_data && (!TARGET_HAVE_MOVT || common_unsupported_modes))
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error ("%s only supports non-pic code on M-profile targets with the "
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"MOVT instruction", flag);
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/* We only support -mpure-code on M-profile targets. */
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if (target_pure_code && common_unsupported_modes)
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error ("%s only supports non-pic code on M-profile targets", flag);
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/* Cannot load addresses: -mslow-flash-data forbids literal pool and
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-mword-relocations forbids relocation of MOVT/MOVW. */
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if (target_word_relocations)
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@ -4421,6 +4426,38 @@ const_ok_for_dimode_op (HOST_WIDE_INT i, enum rtx_code code)
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}
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}
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/* Emit a sequence of movs/adds/shift to produce a 32-bit constant.
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Avoid generating useless code when one of the bytes is zero. */
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void
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thumb1_gen_const_int (rtx op0, HOST_WIDE_INT op1)
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{
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bool mov_done_p = false;
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int i;
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/* Emit upper 3 bytes if needed. */
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for (i = 0; i < 3; i++)
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{
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int byte = (op1 >> (8 * (3 - i))) & 0xff;
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if (byte)
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{
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emit_set_insn (op0, mov_done_p
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? gen_rtx_PLUS (SImode,op0, GEN_INT (byte))
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: GEN_INT (byte));
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mov_done_p = true;
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}
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if (mov_done_p)
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emit_set_insn (op0, gen_rtx_ASHIFT (SImode, op0, GEN_INT (8)));
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}
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/* Emit lower byte if needed. */
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if (!mov_done_p)
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emit_set_insn (op0, GEN_INT (op1 & 0xff));
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else if (op1 & 0xff)
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emit_set_insn (op0, gen_rtx_PLUS (SImode, op0, GEN_INT (op1 & 0xff)));
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}
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/* Emit a sequence of insns to handle a large constant.
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CODE is the code of the operation required, it can be any of SET, PLUS,
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IOR, AND, XOR, MINUS;
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@ -8576,7 +8613,8 @@ thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
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/* This is PC relative data before arm_reorg runs. */
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else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
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&& GET_CODE (x) == SYMBOL_REF
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&& CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
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&& CONSTANT_POOL_ADDRESS_P (x) && !flag_pic
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&& !arm_disable_literal_pool)
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return 1;
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/* This is PC relative data after arm_reorg runs. */
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@ -8644,6 +8682,7 @@ thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
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&& GET_MODE_SIZE (mode) == 4
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&& GET_CODE (x) == SYMBOL_REF
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&& CONSTANT_POOL_ADDRESS_P (x)
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&& !arm_disable_literal_pool
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&& ! (flag_pic
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&& symbol_mentioned_p (get_pool_constant (x))
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&& ! pcrel_constant_p (get_pool_constant (x))))
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@ -9322,7 +9361,9 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
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return 0;
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if (thumb_shiftable_const (INTVAL (x)))
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return COSTS_N_INSNS (2);
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return COSTS_N_INSNS (3);
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return arm_disable_literal_pool
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? COSTS_N_INSNS (8)
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: COSTS_N_INSNS (3);
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}
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else if ((outer == PLUS || outer == COMPARE)
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&& INTVAL (x) < 256 && INTVAL (x) > -256)
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@ -9479,7 +9520,9 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
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/* See split "TARGET_THUMB1 && satisfies_constraint_K". */
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if (thumb_shiftable_const (INTVAL (x)))
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return COSTS_N_INSNS (2);
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return COSTS_N_INSNS (3);
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return arm_disable_literal_pool
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? COSTS_N_INSNS (8)
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: COSTS_N_INSNS (3);
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}
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else if ((outer == PLUS || outer == COMPARE)
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&& INTVAL (x) < 256 && INTVAL (x) > -256)
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@ -27465,14 +27508,41 @@ arm_thumb1_mi_thunk (FILE *file, tree, HOST_WIDE_INT delta,
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/* push r3 so we can use it as a temporary. */
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/* TODO: Omit this save if r3 is not used. */
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fputs ("\tpush {r3}\n", file);
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fputs ("\tldr\tr3, ", file);
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/* With -mpure-code, we cannot load the address from the
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constant pool: we build it explicitly. */
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if (target_pure_code)
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{
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fputs ("\tmovs\tr3, #:upper8_15:#", file);
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assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
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fputc ('\n', file);
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fputs ("\tlsls r3, #8\n", file);
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fputs ("\tadds\tr3, #:upper0_7:#", file);
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assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
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fputc ('\n', file);
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fputs ("\tlsls r3, #8\n", file);
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fputs ("\tadds\tr3, #:lower8_15:#", file);
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assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
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fputc ('\n', file);
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fputs ("\tlsls r3, #8\n", file);
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fputs ("\tadds\tr3, #:lower0_7:#", file);
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assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
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fputc ('\n', file);
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}
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else
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fputs ("\tldr\tr3, ", file);
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}
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else
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{
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fputs ("\tldr\tr12, ", file);
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}
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assemble_name (file, label);
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fputc ('\n', file);
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if (!target_pure_code)
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{
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assemble_name (file, label);
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fputc ('\n', file);
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}
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if (flag_pic)
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{
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/* If we are generating PIC, the ldr instruction below loads
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@ -1857,9 +1857,11 @@ enum arm_auto_incmodes
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for the index in the tablejump instruction. */
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#define CASE_VECTOR_MODE Pmode
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#define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
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|| (TARGET_THUMB1 \
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&& (optimize_size || flag_pic)))
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#define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \
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|| (TARGET_THUMB1 \
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&& (optimize_size || flag_pic))) \
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&& (!target_pure_code))
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#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
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(TARGET_THUMB1 \
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@ -43,6 +43,41 @@
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(define_insn "thumb1_movsi_symbol_ref"
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[(set (match_operand:SI 0 "register_operand" "=l")
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(match_operand:SI 1 "general_operand" ""))
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]
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"TARGET_THUMB1
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&& arm_disable_literal_pool
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&& GET_CODE (operands[1]) == SYMBOL_REF"
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"*
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output_asm_insn (\"movs\\t%0, #:upper8_15:%1\", operands);
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output_asm_insn (\"lsls\\t%0, #8\", operands);
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output_asm_insn (\"adds\\t%0, #:upper0_7:%1\", operands);
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output_asm_insn (\"lsls\\t%0, #8\", operands);
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output_asm_insn (\"adds\\t%0, #:lower8_15:%1\", operands);
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output_asm_insn (\"lsls\\t%0, #8\", operands);
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output_asm_insn (\"adds\\t%0, #:lower0_7:%1\", operands);
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return \"\";
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"
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[(set_attr "length" "14")
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(set_attr "conds" "clob")]
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)
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(match_operand:SI 1 "immediate_operand" ""))]
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"TARGET_THUMB1
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&& arm_disable_literal_pool
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&& GET_CODE (operands[1]) == CONST_INT
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&& !satisfies_constraint_I (operands[1])"
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[(clobber (const_int 0))]
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"
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thumb1_gen_const_int (operands[0], INTVAL (operands[1]));
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DONE;
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"
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)
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(define_insn "*thumb1_adddi3"
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[(set (match_operand:DI 0 "register_operand" "=l")
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(plus:DI (match_operand:DI 1 "register_operand" "%0")
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@ -829,8 +864,8 @@
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(set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
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(define_insn "*thumb1_movhf"
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[(set (match_operand:HF 0 "nonimmediate_operand" "=l,l,m,*r,*h")
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(match_operand:HF 1 "general_operand" "l,mF,l,*h,*r"))]
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[(set (match_operand:HF 0 "nonimmediate_operand" "=l,l,l,m,*r,*h")
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(match_operand:HF 1 "general_operand" "l, m,F,l,*h,*r"))]
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"TARGET_THUMB1
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&& ( s_register_operand (operands[0], HFmode)
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|| s_register_operand (operands[1], HFmode))"
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@ -855,14 +890,34 @@
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}
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return \"ldrh\\t%0, %1\";
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}
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case 2: return \"strh\\t%1, %0\";
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case 2:
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{
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int bits;
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int high;
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rtx ops[3];
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bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]),
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HFmode);
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ops[0] = operands[0];
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high = (bits >> 8) & 0xff;
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ops[1] = GEN_INT (high);
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ops[2] = GEN_INT (bits & 0xff);
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if (high != 0)
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output_asm_insn (\"movs\\t%0, %1\;lsls\\t%0, #8\;adds\\t%0, %2\", ops);
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else
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output_asm_insn (\"movs\\t%0, %2\", ops);
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return \"\";
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}
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case 3: return \"strh\\t%1, %0\";
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default: return \"mov\\t%0, %1\";
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}
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"
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[(set_attr "length" "2")
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(set_attr "type" "mov_reg,load_4,store_4,mov_reg,mov_reg")
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(set_attr "pool_range" "*,1018,*,*,*")
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(set_attr "conds" "clob,nocond,nocond,nocond,nocond")])
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[(set_attr "length" "2,2,6,2,2,2")
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(set_attr "type" "mov_reg,load_4,mov_reg,store_4,mov_reg,mov_reg")
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(set_attr "pool_range" "*,1018,*,*,*,*")
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(set_attr "conds" "clob,nocond,nocond,nocond,nocond,nocond")])
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;;; ??? This should have alternatives for constants.
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(define_insn "*thumb1_movsf_insn"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=l,l,>,l, m,*r,*h")
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@ -18227,8 +18227,7 @@ provided for use in debugging the compiler.
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Do not allow constant data to be placed in code sections.
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Additionally, when compiling for ELF object format give all text sections the
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ELF processor-specific section attribute @code{SHF_ARM_PURECODE}. This option
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is only available when generating non-pic code for M-profile targets with the
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MOVT instruction.
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is only available when generating non-pic code for M-profile targets.
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@item -mcmse
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@opindex mcmse
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@ -1,3 +1,13 @@
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2019-12-17 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/arm/pr45701-1.c: Adjust for -mpure-code.
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* gcc.target/arm/pr45701-2.c: Likewise.
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* gcc.target/arm/pure-code/no-literal-pool.c: Add tests for
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__fp16.
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* gcc.target/arm/pure-code/pure-code.exp: Remove thumb2 and movt
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conditions.
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* gcc.target/arm/thumb1-Os-mult.c: Skip if -mpure-code is used.
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2019-12-17 Andrew Stubbs <ams@codesourcery.com>
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* lib/target-supports.exp
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@ -2,7 +2,7 @@
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/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
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/* { dg-options "-mthumb -Os" } */
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/* { dg-final { scan-assembler "push\t\{r3" { target { ! arm*-*-uclinuxfdpiceabi } } } } */
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/* { dg-final { scan-assembler-not "\[^\-\]r8" { target { ! arm*-*-uclinuxfdpiceabi } } } } */
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/* { dg-final { scan-assembler-not "\[^\-e\]r8" { target { ! arm*-*-uclinuxfdpiceabi } } } } */
|
||||
|
||||
extern int hist_verify;
|
||||
extern int a1;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
|
||||
/* { dg-options "-mthumb -Os" } */
|
||||
/* { dg-final { scan-assembler "push\t\{r3" { target { ! arm*-*-uclinuxfdpiceabi } } } } */
|
||||
/* { dg-final { scan-assembler-not "\[^\-\]r8" { target { ! arm*-*-uclinuxfdpiceabi } } } } */
|
||||
/* { dg-final { scan-assembler-not "\[^\-e\]r8" { target { ! arm*-*-uclinuxfdpiceabi } } } } */
|
||||
|
||||
extern int hist_verify;
|
||||
extern int a1;
|
||||
|
|
|
|||
|
|
@ -1,12 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mpure-code" } */
|
||||
/* { dg-options "-mpure-code -mfp16-format=ieee" } */
|
||||
/* { dg-skip-if "" { *-*-* } { "-g" "-fpic" "-fPIC" } { "" } } */
|
||||
|
||||
__fp16 hf;
|
||||
float sf;
|
||||
double df;
|
||||
long long l;
|
||||
static char *p = "Hello World";
|
||||
|
||||
__fp16
|
||||
testsfp16 (__fp16 *p)
|
||||
{
|
||||
hf = 1.3;
|
||||
*p += hf;
|
||||
if (*p > 1.1234f)
|
||||
return 2.1234f;
|
||||
else
|
||||
return 3.1234f;
|
||||
}
|
||||
|
||||
float
|
||||
testsf (float *p)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -25,11 +25,8 @@ if ![info exists DEFAULT_CFLAGS] then {
|
|||
set DEFAULT_CFLAGS " -ansi -pedantic-errors"
|
||||
}
|
||||
|
||||
# The -mpure-code option is only available for M-profile targets that support
|
||||
# the MOVT instruction.
|
||||
if {([check_effective_target_arm_thumb2_ok]
|
||||
|| [check_effective_target_arm_thumb1_movt_ok])
|
||||
&& [check_effective_target_arm_cortex_m]} then {
|
||||
# The -mpure-code option is only available for M-profile targets.
|
||||
if {[check_effective_target_arm_cortex_m]} then {
|
||||
# Initialize `dg'.
|
||||
dg-init
|
||||
|
||||
|
|
@ -56,4 +53,4 @@ set LTO_TORTURE_OPTIONS ${saved-lto_torture_options}
|
|||
|
||||
# All done.
|
||||
dg-finish
|
||||
}
|
||||
#}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target arm_thumb1_ok } */
|
||||
/* { dg-options "-Os" } */
|
||||
/* { dg-skip-if "-mpure-code generates an inline multiplication code sequence" { *-*-* } { "-mpure-code" } } */
|
||||
/* { dg-skip-if "" { ! { arm_thumb1 } } } */
|
||||
|
||||
int
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue