[APX NDD] Support Intel APX NDD for legacy add insn
APX NDD provides an extra destination register operand for several gpr related legacy insns, so a new alternative can be adopted to operand1 with "r" constraint. This first patch supports NDD for add instruction, and keeps to use lea when all operands are registers since lea have shorter encoding. For add operations containing mem NDD will be adopted to save an extra move. In legacy x86 binary operation expand it will force operands[0] and operands[1] to be the same so add a helper function to allow NDD form pattern that operands[0] and operands[1] can be different. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_fixup_binary_operands): Add new use_ndd flag to check whether ndd can be used for this binop and adjust operand emit. (ix86_binary_operator_ok): Likewise. (ix86_expand_binary_operator): Likewise, and void postreload expand generate lea pattern when use_ndd is explicit parsed. * config/i386/i386-options.cc (ix86_option_override_internal): Prohibit apx subfeatures when not in 64bit mode. * config/i386/i386-protos.h (ix86_binary_operator_ok): Add use_ndd flag. (ix86_fixup_binary_operand): Likewise. (ix86_expand_binary_operand): Likewise. * config/i386/i386.md (*add<mode>_1): Extend with new alternatives to support NDD, and adjust output template. (*addhi_1): Likewise. (*addqi_1): Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-ndd.c: New test.
This commit is contained in:
Kong Lingling
Hongyu Wang
parent
08b7462d3a
commit
e21b2caf6d
5 changed files with 96 additions and 54 deletions
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@ -1260,14 +1260,14 @@ ix86_swap_binary_operands_p (enum rtx_code code, machine_mode mode,
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return false;
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}
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/* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
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destination to use for the operation. If different from the true
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destination in operands[0], a copy operation will be required. */
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destination in operands[0], a copy operation will be required except
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under TARGET_APX_NDD. */
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rtx
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ix86_fixup_binary_operands (enum rtx_code code, machine_mode mode,
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rtx operands[])
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rtx operands[], bool use_ndd)
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{
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rtx dst = operands[0];
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rtx src1 = operands[1];
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@ -1307,7 +1307,7 @@ ix86_fixup_binary_operands (enum rtx_code code, machine_mode mode,
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src1 = force_reg (mode, src1);
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/* Source 1 cannot be a non-matching memory. */
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if (MEM_P (src1) && !rtx_equal_p (dst, src1))
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if (!use_ndd && MEM_P (src1) && !rtx_equal_p (dst, src1))
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src1 = force_reg (mode, src1);
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/* Improve address combine. */
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@ -1338,11 +1338,11 @@ ix86_fixup_binary_operands_no_copy (enum rtx_code code,
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void
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ix86_expand_binary_operator (enum rtx_code code, machine_mode mode,
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rtx operands[])
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rtx operands[], bool use_ndd)
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{
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rtx src1, src2, dst, op, clob;
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dst = ix86_fixup_binary_operands (code, mode, operands);
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dst = ix86_fixup_binary_operands (code, mode, operands, use_ndd);
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src1 = operands[1];
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src2 = operands[2];
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@ -1352,7 +1352,8 @@ ix86_expand_binary_operator (enum rtx_code code, machine_mode mode,
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if (reload_completed
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&& code == PLUS
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&& !rtx_equal_p (dst, src1))
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&& !rtx_equal_p (dst, src1)
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&& !use_ndd)
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{
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/* This is going to be an LEA; avoid splitting it later. */
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emit_insn (op);
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@ -1451,7 +1452,7 @@ ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode,
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bool
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ix86_binary_operator_ok (enum rtx_code code, machine_mode mode,
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rtx operands[3])
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rtx operands[3], bool use_ndd)
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{
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rtx dst = operands[0];
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rtx src1 = operands[1];
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@ -1475,7 +1476,7 @@ ix86_binary_operator_ok (enum rtx_code code, machine_mode mode,
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return false;
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/* Source 1 cannot be a non-matching memory. */
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if (MEM_P (src1) && !rtx_equal_p (dst, src1))
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if (!use_ndd && MEM_P (src1) && !rtx_equal_p (dst, src1))
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/* Support "andhi/andsi/anddi" as a zero-extending move. */
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return (code == AND
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&& (mode == HImode
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@ -2129,6 +2129,8 @@ ix86_option_override_internal (bool main_args_p,
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if (TARGET_APX_F && !TARGET_64BIT)
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error ("%<-mapxf%> is not supported for 32-bit code");
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else if (opts->x_ix86_apx_features != apx_none && !TARGET_64BIT)
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error ("%<-mapx-features=%> option is not supported for 32-bit code");
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if (TARGET_UINTR && !TARGET_64BIT)
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error ("%<-muintr%> not supported for 32-bit code");
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@ -108,14 +108,14 @@ extern void ix86_expand_move (machine_mode, rtx[]);
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extern void ix86_expand_vector_move (machine_mode, rtx[]);
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extern void ix86_expand_vector_move_misalign (machine_mode, rtx[]);
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extern rtx ix86_fixup_binary_operands (enum rtx_code,
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machine_mode, rtx[]);
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machine_mode, rtx[], bool = false);
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extern void ix86_fixup_binary_operands_no_copy (enum rtx_code,
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machine_mode, rtx[]);
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extern void ix86_expand_binary_operator (enum rtx_code,
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machine_mode, rtx[]);
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machine_mode, rtx[], bool = false);
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extern void ix86_expand_vector_logical_operator (enum rtx_code,
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machine_mode, rtx[]);
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extern bool ix86_binary_operator_ok (enum rtx_code, machine_mode, rtx[3]);
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extern bool ix86_binary_operator_ok (enum rtx_code, machine_mode, rtx[3], bool = false);
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extern bool ix86_avoid_lea_for_add (rtx_insn *, rtx[]);
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extern bool ix86_use_lea_for_mov (rtx_insn *, rtx[]);
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extern bool ix86_avoid_lea_for_addr (rtx_insn *, rtx[]);
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@ -562,7 +562,7 @@
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;; Used to control the "enabled" attribute on a per-instruction basis.
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(define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx,
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x64_avx,x64_avx512bw,x64_avx512dq,aes,
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x64_avx,x64_avx512bw,x64_avx512dq,aes,apx_ndd,
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sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
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avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,avx512f_512,
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noavx512f,avx512bw,avx512bw_512,noavx512bw,avx512dq,
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@ -960,6 +960,8 @@
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(symbol_ref "TARGET_AVX512BF16 && TARGET_AVX512VL")
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(eq_attr "isa" "vpclmulqdqvl")
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(symbol_ref "TARGET_VPCLMULQDQ && TARGET_AVX512VL")
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(eq_attr "isa" "apx_ndd")
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(symbol_ref "TARGET_APX_NDD")
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(eq_attr "mmx_isa" "native")
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(symbol_ref "!TARGET_MMX_WITH_SSE")
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@ -6288,7 +6290,8 @@
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(plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")
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(match_operand:SDWIM 2 "<general_hilo_operand>")))]
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""
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"ix86_expand_binary_operator (PLUS, <MODE>mode, operands); DONE;")
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"ix86_expand_binary_operator (PLUS, <MODE>mode, operands,
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TARGET_APX_NDD); DONE;")
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(define_insn_and_split "*add<dwi>3_doubleword"
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[(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
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@ -6415,26 +6418,29 @@
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"split_double_mode (<DWI>mode, &operands[0], 1, &operands[0], &operands[5]);")
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(define_insn "*add<mode>_1"
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r")
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r,r,r")
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(plus:SWI48
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(match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r")
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(match_operand:SWI48 2 "x86_64_general_operand" "re,BM,0,le")))
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(match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r,rm,r")
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(match_operand:SWI48 2 "x86_64_general_operand" "re,BM,0,le,re,BM")))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
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"ix86_binary_operator_ok (PLUS, <MODE>mode, operands,
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TARGET_APX_NDD)"
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{
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bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
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switch (get_attr_type (insn))
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{
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case TYPE_LEA:
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return "#";
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case TYPE_INCDEC:
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gcc_assert (rtx_equal_p (operands[0], operands[1]));
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if (operands[2] == const1_rtx)
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return "inc{<imodesuffix>}\t%0";
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return use_ndd ? "inc{<imodesuffix>}\t{%1, %0|%0, %1}"
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: "inc{<imodesuffix>}\t%0";
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else
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{
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gcc_assert (operands[2] == constm1_rtx);
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return "dec{<imodesuffix>}\t%0";
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return use_ndd ? "dec{<imodesuffix>}\t{%1, %0|%0, %1}"
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: "dec{<imodesuffix>}\t%0";
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}
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default:
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@ -6443,14 +6449,16 @@
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if (which_alternative == 2)
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std::swap (operands[1], operands[2]);
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gcc_assert (rtx_equal_p (operands[0], operands[1]));
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if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
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return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
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return use_ndd ? "sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
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: "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
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return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
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return use_ndd ? "add{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
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: "add{<imodesuffix>}\t{%2, %0|%0, %2}";
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}
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}
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[(set (attr "type")
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[(set_attr "isa" "*,*,*,*,apx_ndd,apx_ndd")
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(set (attr "type")
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(cond [(eq_attr "alternative" "3")
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(const_string "lea")
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(match_operand:SWI48 2 "incdec_operand")
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@ -6519,25 +6527,26 @@
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(set_attr "mode" "SI")])
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(define_insn "*addhi_1"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r,Yp")
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(plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r,Yp")
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(match_operand:HI 2 "general_operand" "rn,m,0,ln")))
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[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r,Yp,r,r")
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(plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r,Yp,rm,r")
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(match_operand:HI 2 "general_operand" "rn,m,0,ln,rn,m")))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (PLUS, HImode, operands)"
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"ix86_binary_operator_ok (PLUS, HImode, operands,
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TARGET_APX_NDD)"
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{
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bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
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switch (get_attr_type (insn))
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{
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case TYPE_LEA:
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return "#";
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case TYPE_INCDEC:
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gcc_assert (rtx_equal_p (operands[0], operands[1]));
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if (operands[2] == const1_rtx)
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return "inc{w}\t%0";
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return use_ndd ? "inc{w}\t{%1, %0|%0, %1}" : "inc{w}\t%0";
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else
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{
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gcc_assert (operands[2] == constm1_rtx);
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return "dec{w}\t%0";
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return use_ndd ? "dec{w}\t{%1, %0|%0, %1}" : "dec{w}\t%0";
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}
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default:
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@ -6546,14 +6555,16 @@
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if (which_alternative == 2)
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std::swap (operands[1], operands[2]);
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gcc_assert (rtx_equal_p (operands[0], operands[1]));
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if (x86_maybe_negate_const_int (&operands[2], HImode))
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return "sub{w}\t{%2, %0|%0, %2}";
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return use_ndd ? "sub{w}\t{%2, %1, %0|%0, %1, %2}"
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: "sub{w}\t{%2, %0|%0, %2}";
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return "add{w}\t{%2, %0|%0, %2}";
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return use_ndd ? "add{w}\t{%2, %1, %0|%0, %1, %2}"
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: "add{w}\t{%2, %0|%0, %2}";
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}
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}
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[(set (attr "type")
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[(set_attr "isa" "*,*,*,*,apx_ndd,apx_ndd")
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(set (attr "type")
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(cond [(eq_attr "alternative" "3")
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(const_string "lea")
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(match_operand:HI 2 "incdec_operand")
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@ -6565,30 +6576,35 @@
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(and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
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(const_string "1")
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(const_string "*")))
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(set_attr "mode" "HI,HI,HI,SI")])
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(set_attr "mode" "HI,HI,HI,SI,HI,HI")])
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(define_insn "*addqi_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,q,r,r,Yp")
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(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,q,0,r,Yp")
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(match_operand:QI 2 "general_operand" "qn,m,0,rn,0,ln")))
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,q,r,r,Yp,r,r")
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(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,q,0,r,Yp,rm,r")
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(match_operand:QI 2 "general_operand" "qn,m,0,rn,0,ln,rn,m")))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (PLUS, QImode, operands)"
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"ix86_binary_operator_ok (PLUS, QImode, operands, TARGET_APX_NDD)"
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{
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bool widen = (get_attr_mode (insn) != MODE_QI);
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bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
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switch (get_attr_type (insn))
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{
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case TYPE_LEA:
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return "#";
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case TYPE_INCDEC:
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gcc_assert (rtx_equal_p (operands[0], operands[1]));
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if (operands[2] == const1_rtx)
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return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
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if (use_ndd)
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return "inc{b}\t{%1, %0|%0, %1}";
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else
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return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
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else
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{
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gcc_assert (operands[2] == constm1_rtx);
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return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
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if (use_ndd)
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return "dec{b}\t{%1, %0|%0, %1}";
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else
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return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
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}
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default:
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@ -6597,21 +6613,23 @@
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if (which_alternative == 2 || which_alternative == 4)
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std::swap (operands[1], operands[2]);
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gcc_assert (rtx_equal_p (operands[0], operands[1]));
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if (x86_maybe_negate_const_int (&operands[2], QImode))
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{
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if (widen)
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return "sub{l}\t{%2, %k0|%k0, %2}";
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if (use_ndd)
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return "sub{b}\t{%2, %1, %0|%0, %1, %2}";
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else
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return "sub{b}\t{%2, %0|%0, %2}";
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return widen ? "sub{l}\t{%2, %k0|%k0, %2}"
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: "sub{b}\t{%2, %0|%0, %2}";
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}
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if (widen)
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return "add{l}\t{%k2, %k0|%k0, %k2}";
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if (use_ndd)
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return "add{b}\t{%2, %1, %0|%0, %1, %2}";
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else
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return "add{b}\t{%2, %0|%0, %2}";
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return widen ? "add{l}\t{%k2, %k0|%k0, %k2}"
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: "add{b}\t{%2, %0|%0, %2}";
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}
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}
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[(set (attr "type")
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[(set_attr "isa" "*,*,*,*,*,*,apx_ndd,apx_ndd")
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(set (attr "type")
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(cond [(eq_attr "alternative" "5")
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(const_string "lea")
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(match_operand:QI 2 "incdec_operand")
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@ -6623,7 +6641,7 @@
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(and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
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(const_string "1")
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(const_string "*")))
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(set_attr "mode" "QI,QI,QI,SI,SI,SI")
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(set_attr "mode" "QI,QI,QI,SI,SI,SI,QI,QI")
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;; Potential partial reg stall on alternatives 3 and 4.
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(set (attr "preferred_for_speed")
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(cond [(eq_attr "alternative" "3,4")
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21
gcc/testsuite/gcc.target/i386/apx-ndd.c
Normal file
21
gcc/testsuite/gcc.target/i386/apx-ndd.c
Normal file
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@ -0,0 +1,21 @@
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/* { dg-do compile { target { ! ia32 } } } */
|
||||
/* { dg-options "-mapxf -march=x86-64 -O2" } */
|
||||
/* { dg-final { scan-assembler-not "movl"} } */
|
||||
|
||||
int foo (int *a)
|
||||
{
|
||||
int b = *a - 1;
|
||||
return b;
|
||||
}
|
||||
|
||||
int foo2 (int a, int b)
|
||||
{
|
||||
int c = a + b;
|
||||
return c;
|
||||
}
|
||||
|
||||
int foo3 (int *a, int b)
|
||||
{
|
||||
int c = *a + b;
|
||||
return c;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue