re PR target/16457 (PowerPC - Combine two rldicr instructions into a single rlwinm.)
.: PR target/16457 * config/rs6000/rs6000.c (mask64_2_operand): Stub to call mask64_1or2_operand. (mask64_1or_2_operand): Broken out of mask64_2_operand, add flag to spot rlwinm opportunities. (and64_2_operand): Use mask_1or2_operand. * config/rs6000/rs6000.md (anddi3): Use rlwinm when possible. testsuite: PR target/16457 * gcc.dg/ppc-and-1: New From-SVN: r90481
This commit is contained in:
Nathan Sidwell
Nathan Sidwell
parent
00803cd56f
commit
e1e2e653d7
5 changed files with 64 additions and 17 deletions
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@ -1,3 +1,13 @@
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2004-11-11 Nathan Sidwell <nathan@codesourcery.com>
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PR target/16457
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* config/rs6000/rs6000.c (mask64_2_operand): Stub to call
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mask64_1or2_operand.
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(mask64_1or2_operand): Broken out of mask64_2_operand, add flag
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to spot rlwinm opportunities.
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(and64_2_operand): Use mask_1or2_operand.
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* config/rs6000/rs6000.md (anddi3): Use rlwinm when possible.
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2004-11-11 Dorit Naishlos <dorit@il.ibm.com>
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* tree-vectorizer.c (update_phi_nodes_for_guard): Call reverse_phis.
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@ -2708,23 +2708,26 @@ mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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return 0;
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}
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/* Like mask64_operand, but allow up to three transitions. This
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predicate is used by insn patterns that generate two rldicl or
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rldicr machine insns. */
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int
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mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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static int
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mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
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bool allow_one)
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{
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if (GET_CODE (op) == CONST_INT)
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{
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HOST_WIDE_INT c, lsb;
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bool one_ok;
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c = INTVAL (op);
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/* Disallow all zeros. */
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if (c == 0)
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return 0;
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/* We can use a single rlwinm insn if no upper bits of C are set
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AND there are zero, one or two transitions in the _whole_ of
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C. */
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one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
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/* We don't change the number of transitions by inverting,
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so make sure we start with the LS bit zero. */
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if (c & 1)
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@ -2748,6 +2751,9 @@ mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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/* Erase second transition. */
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c &= -lsb;
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if (one_ok && !(allow_one || c))
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return 0;
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/* Find the third transition (if any). */
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lsb = c & -c;
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@ -2757,6 +2763,14 @@ mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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return 0;
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}
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/* Like mask64_operand, but allow up to three transitions. This
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predicate is used by insn patterns that generate two rldicl or
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rldicr machine insns. */
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int mask64_2_operand (rtx op, enum machine_mode mode)
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{
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return mask64_1or2_operand (op, mode, false);
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}
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/* Generates shifts and masks for a pair of rldicl or rldicr insns to
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implement ANDing by the mask IN. */
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void
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@ -2846,9 +2860,9 @@ int
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and64_2_operand (rtx op, enum machine_mode mode)
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{
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if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
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return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
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return gpc_reg_operand (op, mode) || mask64_1or2_operand (op, mode, true);
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return logical_operand (op, mode) || mask64_2_operand (op, mode);
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return logical_operand (op, mode) || mask64_1or2_operand (op, mode, true);
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}
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/* Return 1 if the operand is either a non-special register or a
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@ -7197,19 +7197,20 @@
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"")
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(define_insn "anddi3"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
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(and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
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(match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
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(clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
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(and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
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(match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
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(clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
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"TARGET_POWERPC64"
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"@
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and %0,%1,%2
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rldic%B2 %0,%1,0,%S2
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rlwinm %0,%1,0,%m2,%M2
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andi. %0,%1,%b2
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andis. %0,%1,%u2
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#"
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[(set_attr "type" "*,*,compare,compare,*")
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(set_attr "length" "4,4,4,4,8")])
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[(set_attr "type" "*,*,*,compare,compare,*")
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(set_attr "length" "4,4,4,4,4,8")])
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(define_split
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[(set (match_operand:DI 0 "gpc_reg_operand" "")
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@ -7227,10 +7228,9 @@
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(and:DI (rotate:DI (match_dup 0)
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(match_dup 6))
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(match_dup 7)))]
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"
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{
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build_mask64_2_operands (operands[2], &operands[4]);
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}")
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})
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(define_insn "*anddi3_internal2"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
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@ -1,5 +1,8 @@
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2004-11-11 Nathan Sidwell <nathan@codesourcery.com>
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PR target/16457
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* gcc.dg/ppc-and-1: New
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PR target/16796
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* gcc.dg/ppc-mov-1.c: New.
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20
gcc/testsuite/gcc.dg/ppc-and-1.c
Normal file
20
gcc/testsuite/gcc.dg/ppc-and-1.c
Normal file
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@ -0,0 +1,20 @@
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/* { dg-do compile { target powerpc64-*-* } } */
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/* { dg-options "-m64 -O2" } */
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/* { dg-final { scan-assembler "rlwinm \[0-9\]+,\[0-9\]+,0,0,30" } } */
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/* { dg-final { scan-assembler "rlwinm \[0-9\]+,\[0-9\]+,0,29,30" } } */
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/* { dg-final { scan-assembler-not "rldicr" } } */
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/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
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/* PR 16457 - use rlwinm insn. */
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char *foo1 (char *p, unsigned int x)
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{
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return p - (x & ~1);
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}
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char *foo2 (char *p, unsigned int x)
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{
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return p - (x & 6);
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}
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