mips.h (ISA_HAS_SYNCI): New target capability predicate.
2007-07-10 David Daney <ddaney@avtrex.com> * config/mips/mips.h (ISA_HAS_SYNCI): New target capability predicate. (INITIALIZE_TRAMPOLINE): Emit clear_cache insn instead of library call. * config/mips/mips.c (mips_expand_synci_loop): New function. * config/mips/mips.md (UNSPEC_CLEAR_HAZARD): New constant. (UNSPEC_RDHWR): Same. (UNSPEC_SYNCI): Same. (UNSPEC_SYNC): Same. (clear_cache): New expand. (sync): New insn. (synci): Same. (rdhwr): Same. (clear_hazard): Same. * config/mips/mips-protos.h (mips_expand_synci_loop): Declare function. * testsuite/gcc.target/mips/clear-cache-1.c: New test. * testsuite/gcc.target/mips/clear-cache-2.c: New test. From-SVN: r126537
This commit is contained in:
David Daney
David Daney
parent
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commit
df770e0442
7 changed files with 152 additions and 11 deletions
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@ -1,3 +1,24 @@
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2007-07-10 David Daney <ddaney@avtrex.com>
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* config/mips/mips.h (ISA_HAS_SYNCI): New target capability
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predicate.
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(INITIALIZE_TRAMPOLINE): Emit clear_cache insn instead of library
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call.
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* config/mips/mips.c (mips_expand_synci_loop): New function.
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* config/mips/mips.md (UNSPEC_CLEAR_HAZARD): New constant.
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(UNSPEC_RDHWR): Same.
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(UNSPEC_SYNCI): Same.
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(UNSPEC_SYNC): Same.
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(clear_cache): New expand.
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(sync): New insn.
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(synci): Same.
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(rdhwr): Same.
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(clear_hazard): Same.
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* config/mips/mips-protos.h (mips_expand_synci_loop): Declare
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function.
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* testsuite/gcc.target/mips/clear-cache-1.c: New test.
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* testsuite/gcc.target/mips/clear-cache-2.c: New test.
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2007-07-10 Ian Lance Taylor <iant@google.com>
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* emit-rtl.c (gen_reg_rtx): Check can_create_pseudo_p rather than
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@ -1,6 +1,6 @@
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/* Prototypes of target machine for GNU compiler. MIPS version.
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Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
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1999, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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1999, 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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Contributed by A. Lichnewsky (lich@inria.inria.fr).
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Changed by Michael Meissner (meissner@osf.org).
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64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
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@ -187,6 +187,7 @@ extern void mips_expand_call (rtx, rtx, rtx, rtx, int);
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extern void mips_emit_fcc_reload (rtx, rtx, rtx);
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extern void mips_set_return_address (rtx, rtx);
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extern bool mips_expand_block_move (rtx, rtx, rtx);
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extern void mips_expand_synci_loop (rtx, rtx);
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extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx);
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extern void function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
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@ -3883,6 +3883,33 @@ mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
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mips_block_move_straight (dest, src, leftover);
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}
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/* Expand a loop of synci insns for the address range [BEGIN, END). */
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void
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mips_expand_synci_loop (rtx begin, rtx end)
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{
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rtx inc, label, cmp, cmp_result;
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/* Load INC with the cache line size (rdhwr INC,$1). */
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inc = gen_reg_rtx (SImode);
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emit_insn (gen_rdhwr (inc, const1_rtx));
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/* Loop back to here. */
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label = gen_label_rtx ();
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emit_label (label);
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emit_insn (gen_synci (begin));
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cmp = gen_reg_rtx (Pmode);
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mips_emit_binary (GTU, cmp, begin, end);
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mips_emit_binary (PLUS, begin, begin, inc);
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cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
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emit_jump_insn (gen_condjump (cmp_result, label));
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}
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/* Expand a movmemsi instruction. */
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bool
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@ -804,6 +804,10 @@ extern const struct mips_rtx_cost_data *mips_cost;
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|| ISA_MIPS32R2 \
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|| ISA_MIPS64 \
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|| TARGET_MIPS5500)
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/* ISA includes synci, jr.hb and jalr.hb. */
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#define ISA_HAS_SYNCI ISA_MIPS32R2
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/* Add -G xx support. */
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@ -2151,21 +2155,16 @@ typedef struct mips_args {
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#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
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{ \
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rtx func_addr, chain_addr; \
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rtx func_addr, chain_addr, end_addr; \
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\
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func_addr = plus_constant (ADDR, 32); \
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chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
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emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
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emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
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\
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/* Flush both caches. We need to flush the data cache in case \
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the system has a write-back cache. */ \
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/* ??? Should check the return value for errors. */ \
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if (mips_cache_flush_func && mips_cache_flush_func[0]) \
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emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
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0, VOIDmode, 3, ADDR, Pmode, \
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GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
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GEN_INT (3), TYPE_MODE (integer_type_node)); \
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end_addr = gen_reg_rtx (Pmode); \
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emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
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GEN_INT (TRAMPOLINE_SIZE))); \
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emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
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}
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/* Addressing modes, and classification of registers for them. */
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@ -50,6 +50,10 @@
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(UNSPEC_TLS_GET_TP 28)
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(UNSPEC_MFHC1 31)
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(UNSPEC_MTHC1 32)
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(UNSPEC_CLEAR_HAZARD 33)
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(UNSPEC_RDHWR 34)
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(UNSPEC_SYNCI 35)
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(UNSPEC_SYNC 36)
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(UNSPEC_ADDRESS_FIRST 100)
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@ -4221,6 +4225,69 @@
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}
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[(set_attr "type" "store")
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(set_attr "length" "4,12")])
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;; Expand in-line code to clear the instruction cache between operand[0] and
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;; operand[1].
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(define_expand "clear_cache"
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[(match_operand 0 "pmode_register_operand")
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(match_operand 1 "pmode_register_operand")]
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""
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"
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{
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if (ISA_HAS_SYNCI)
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{
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mips_expand_synci_loop (operands[0], operands[1]);
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emit_insn (gen_sync ());
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emit_insn (gen_clear_hazard ());
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}
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else if (mips_cache_flush_func && mips_cache_flush_func[0])
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{
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rtx len = gen_reg_rtx (Pmode);
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emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
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/* Flush both caches. We need to flush the data cache in case
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the system has a write-back cache. */
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emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func),
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0, VOIDmode, 3, operands[0], Pmode,
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len, TYPE_MODE (integer_type_node),
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GEN_INT (3), TYPE_MODE (integer_type_node));
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}
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DONE;
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}")
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(define_insn "sync"
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[(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
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"ISA_HAS_SYNCI"
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"sync")
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(define_insn "synci"
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[(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
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UNSPEC_SYNCI)]
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"ISA_HAS_SYNCI"
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"synci\t0(%0)")
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(define_insn "rdhwr"
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[(set (match_operand:SI 0 "general_operand" "=d")
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(unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
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UNSPEC_RDHWR))]
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"ISA_HAS_SYNCI"
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"rdhwr\t%0,$%1")
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(define_insn "clear_hazard"
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[(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
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(clobber (reg:SI 31))]
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"ISA_HAS_SYNCI"
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{
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return ".set\tpush\n"
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"\t.set\tnoreorder\n"
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"\t.set\tnomacro\n"
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"\tbal\t1f\n"
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"\tnop\n"
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"1:\taddiu\t$31,$31,12\n"
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"\tjr.hb\t$31\n"
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"\tnop\n"
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"\t.set\tpop";
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}
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[(set_attr "length" "20")])
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;; Block moves, see mips.c for more details.
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;; Argument 0 is the destination
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13
gcc/testsuite/gcc.target/mips/clear-cache-1.c
Normal file
13
gcc/testsuite/gcc.target/mips/clear-cache-1.c
Normal file
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@ -0,0 +1,13 @@
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/* { dg-do compile } */
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/* { dg-mips-options "-O2 -mips32r2" } */
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/* { dg-final { scan-assembler "synci" } } */
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/* { dg-final { scan-assembler "jr.hb" } } */
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/* { dg-final { scan-assembler-not "_flush_cache" } } */
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void f()
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{
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int size = 40;
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char *memory = __builtin_alloca(size);
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__builtin___clear_cache(memory, memory + size);
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}
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13
gcc/testsuite/gcc.target/mips/clear-cache-2.c
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13
gcc/testsuite/gcc.target/mips/clear-cache-2.c
Normal file
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@ -0,0 +1,13 @@
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/* { dg-do compile } */
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/* { dg-mips-options "-O2 -mips32" } */
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/* { dg-final { scan-assembler-not "synci" } } */
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/* { dg-final { scan-assembler-not "jr.hb" } } */
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/* { dg-final { scan-assembler "_flush_cache" } } */
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void f()
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{
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int size = 40;
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char *memory = __builtin_alloca(size);
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__builtin___clear_cache(memory, memory + size);
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}
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