FreeChainXenon/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

config.gcc: Add crx-elf support.

Browse source 
* config.gcc: Add crx-elf support.

        * doc/contrib.texi: Mention crx.
        * doc/extend.texi: Document crx extensions.
        * doc/install.texi: Document crx install.
        * doc/invoke.texi: Document crx options.
        * doc/md.texi: Document crx constraints.

        * config/crx/crx-protos.h: New file.
        * config/crx/crx.c: New file.
        * config/crx/crx.h: New file.
        * config/crx/crx.md: New file.
        * config/crx/crx.opt: New file.
        * config/crx/t-crx: New file.

From-SVN: r102278
This commit is contained in:
Paul Woegerer 2005-07-22 09:49:48 +00:00 • committed by Paul Woegerer
parent 0fb6f88ac7
commit db8697336f
8 changed files with 3082 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
gcc/ChangeLog
View file

@ -1,3 +1,20 @@
2005-07-22 Paul Woegerer <paul.woegerer@nsc.com>
* config.gcc: Add crx-elf support.
* doc/contrib.texi: Mention crx.
* doc/extend.texi: Document crx extensions.
* doc/install.texi: Document crx install.
* doc/invoke.texi: Document crx options.
* doc/md.texi: Document crx constraints.
* config/crx/crx-protos.h: New file.
* config/crx/crx.c: New file.
* config/crx/crx.h: New file.
* config/crx/crx.md: New file.
* config/crx/crx.opt: New file.
* config/crx/t-crx: New file.
2005-07-22 Manfred Hollstein <mh@suse.com>
* tree-ssa-structalias.c (merge_graph_nodes): Fix uninitialised

5
gcc/config.gcc
View file

@ -779,6 +779,11 @@ cris-*-linux*)
tmake_file="cris/t-cris t-slibgcc-elf-ver cris/t-linux"
extra_options="${extra_options} cris/linux.opt"
;;
crx-*-elf)
tm_file="elfos.h ${tm_file}"
extra_parts="crtbegin.o crtend.o"
use_collect2=no
;;
fr30-*-elf)
tm_file="dbxelf.h elfos.h svr4.h ${tm_file}"
tmake_file=fr30/t-fr30

75
gcc/config/crx/crx-protos.h Normal file
View file

@ -0,0 +1,75 @@
/* Prototypes for exported functions defined in crx.c
Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
2002, 2003, 2004 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 2, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#ifndef GCC_CRX_PROTOS_H
#define GCC_CRX_PROTOS_H
/* Register usage. */
extern enum reg_class crx_regno_reg_class (int);
extern int crx_hard_regno_mode_ok (int regno, enum machine_mode);
#ifdef RTX_CODE
extern enum reg_class crx_secondary_reload_class (enum reg_class, enum machine_mode, rtx);
#endif /* RTX_CODE */
/* Passing function arguments. */
extern int crx_function_arg_regno_p (int);
#ifdef TREE_CODE
extern void crx_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
#ifdef RTX_CODE
extern void crx_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx);
extern rtx crx_function_arg (struct cumulative_args *, enum machine_mode, tree, int);
#endif /* RTX_CODE */
#endif /* TREE_CODE */
#ifdef RTX_CODE
/* Addressing Modes. */
extern int crx_legitimate_address_p (enum machine_mode, rtx, int);
extern int crx_const_double_ok (rtx op);
/* Instruction output. */
extern void crx_print_operand (FILE *, rtx, int);
extern void crx_print_operand_address (FILE *, rtx);
/* Misc functions called from crx.md. */
extern rtx crx_expand_compare (enum rtx_code, enum machine_mode);
extern void crx_expand_branch (enum rtx_code, rtx);
extern void crx_expand_scond (enum rtx_code, rtx);
extern void crx_expand_movmem_single (rtx, rtx, rtx, rtx, rtx, unsigned HOST_WIDE_INT *);
extern int crx_expand_movmem (rtx, rtx, rtx, rtx);
#endif /* RTX_CODE */
/* Routines to compute costs. */
extern int crx_memory_move_cost (enum machine_mode, enum reg_class, int);
/* Prologue/Epilogue functions. */
extern int crx_initial_elimination_offset (int, int);
extern char *crx_prepare_push_pop_string (int);
extern void crx_expand_prologue (void);
extern void crx_expand_epilogue (void);
/* Handling the "interrupt" attribute */
extern int crx_interrupt_function_p (void);
#endif /* GCC_CRX_PROTOS_H */

1485
gcc/config/crx/crx.c Normal file
View file

File diff suppressed because it is too large Load diff

533
gcc/config/crx/crx.h Normal file
View file

@ -0,0 +1,533 @@
/* Definitions of target machine for GNU compiler, for CRX.
Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
2001, 2002, 2003, 2004 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 2, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
MA 02111-1307, USA. */
#ifndef GCC_CRX_H
#define GCC_CRX_H
/*****************************************************************************/
/* CONTROLLING THE DRIVER */
/*****************************************************************************/
#define CC1PLUS_SPEC "%{!frtti:-fno-rtti} \
%{!fenforce-eh-specs:-fno-enforce-eh-specs} \
%{!fexceptions:-fno-exceptions} \
%{!fthreadsafe-statics:-fno-threadsafe-statics}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "crti.o%s crtbegin.o%s"
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
/*****************************************************************************/
/* RUN-TIME TARGET SPECIFICATION */
/*****************************************************************************/
#ifndef TARGET_CPU_CPP_BUILTINS
#define TARGET_CPU_CPP_BUILTINS() \
do { \
builtin_define("__CRX__"); \
builtin_define("__CR__"); \
} while (0)
#endif
#define TARGET_VERSION fputs (" (CRX/ELF)", stderr);
/* Put each function in its own section so that PAGE-instruction
* relaxation can do its best. */
#define OPTIMIZATION_OPTIONS(LEVEL, SIZEFLAG) \
do { \
if ((LEVEL) || (SIZEFLAG)) \
flag_function_sections = 1; \
} while (0)
/* Show we can debug even without a frame pointer. */
#define CAN_DEBUG_WITHOUT_FP
/*****************************************************************************/
/* STORAGE LAYOUT */
/*****************************************************************************/
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN 0
#define WORDS_BIG_ENDIAN 0
#define UNITS_PER_WORD 4
#define POINTER_SIZE 32
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY 32
#define FUNCTION_BOUNDARY 32
#define STRUCTURE_SIZE_BOUNDARY 32
#define BIGGEST_ALIGNMENT 32
/* In CRX arrays of chars are word-aligned, so strcpy() will be faster. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == ARRAY_TYPE && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < BITS_PER_WORD \
? (BITS_PER_WORD) : (ALIGN))
/* In CRX strings are word-aligned so strcpy from constants will be faster. */
#define CONSTANT_ALIGNMENT(CONSTANT, ALIGN) \
(TREE_CODE (CONSTANT) == STRING_CST && (ALIGN) < BITS_PER_WORD \
? (BITS_PER_WORD) : (ALIGN))
#define STRICT_ALIGNMENT 0
#define PCC_BITFIELD_TYPE_MATTERS 1
/*****************************************************************************/
/* LAYOUT OF SOURCE LANGUAGE DATA TYPES */
/*****************************************************************************/
#define INT_TYPE_SIZE 32
#define SHORT_TYPE_SIZE 16
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE 64
#define DEFAULT_SIGNED_CHAR 1
#define SIZE_TYPE "unsigned int"
#define PTRDIFF_TYPE "int"
/*****************************************************************************/
/* REGISTER USAGE. */
/*****************************************************************************/
#define FIRST_PSEUDO_REGISTER 19
/* On the CRX, only the stack pointer (r15) is such. */
#define FIXED_REGISTERS \
{ \
/* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* r11 r12 r13 ra sp r16 r17 cc */ \
0, 0, 0, 0, 1, 0, 0, 1 \
}
/* On the CRX, calls clobbers r0-r6 (scratch registers), ra (the return address)
* and sp - (the stack pointer which is fixed). */
#define CALL_USED_REGISTERS \
{ \
/* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 */ \
1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
/* r11 r12 r13 ra sp r16 r17 cc */ \
0, 0, 0, 1, 1, 1, 1, 1 \
}
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* On the CRX architecture, HILO regs can only hold SI mode. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) crx_hard_regno_mode_ok(REGNO, MODE)
/* So far no patterns for moving CCMODE data are available */
#define AVOID_CCMODE_COPIES
/* Interrupt functions can only use registers that have already been saved by
* the prologue, even if they would normally be call-clobbered. */
#define HARD_REGNO_RENAME_OK(SRC, DEST) \
(!crx_interrupt_function_p () || regs_ever_live[DEST])
#define MODES_TIEABLE_P(MODE1, MODE2) 1
enum reg_class
{
NO_REGS,
LO_REGS,
HI_REGS,
HILO_REGS,
NOSP_REGS,
GENERAL_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"LO_REGS", \
"HI_REGS", \
"HILO_REGS", \
"NOSP_REGS", \
"GENERAL_REGS", \
"ALL_REGS" \
}
#define REG_CLASS_CONTENTS \
{ \
{0x00000000}, /* NO_REGS */ \
{0x00010000}, /* LO_REGS : 16 */ \
{0x00020000}, /* HI_REGS : 17 */ \
{0x00030000}, /* HILO_REGS : 16, 17 */ \
{0x00007fff}, /* NOSP_REGS : 0 - 14 */ \
{0x0000ffff}, /* GENERAL_REGS : 0 - 15 */ \
{0x0007ffff} /* ALL_REGS : 0 - 18 */ \
}
#define REGNO_REG_CLASS(REGNO) crx_regno_reg_class(REGNO)
#define BASE_REG_CLASS GENERAL_REGS
#define INDEX_REG_CLASS GENERAL_REGS
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'b' ? NOSP_REGS : \
(C) == 'l' ? LO_REGS : \
(C) == 'h' ? HI_REGS : \
(C) == 'k' ? HILO_REGS : \
NO_REGS)
#define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) < 16 \
|| (reg_renumber && (unsigned)reg_renumber[REGNO] < 16))
#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
#define REGNO_OK_FOR_INDEXED_BASE_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
crx_secondary_reload_class (CLASS, MODE, X)
#define CLASS_MAX_NREGS(CLASS, MODE) \
(GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD
#define SIGNED_INT_FITS_N_BITS(imm, N) \
((((imm) < ((long long)1<<((N)-1))) && ((imm) >= -((long long)1<<((N)-1)))) ? 1 : 0)
#define UNSIGNED_INT_FITS_N_BITS(imm, N) \
(((imm) < ((long long)1<<(N)) && (imm) >= (long long)0) ? 1 : 0)
#define HILO_REGNO_P(regno) \
(reg_classes_intersect_p(REGNO_REG_CLASS(regno), HILO_REGS))
#define INT_CST4(VALUE) \
(((VALUE) >= -1 && (VALUE) <= 4) || (VALUE) == -4 \
|| (VALUE) == 7 || (VALUE) == 8 || (VALUE) == 16 || (VALUE) == 32 \
|| (VALUE) == 20 || (VALUE) == 12 || (VALUE) == 48)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
/* Legal const for store immediate instructions */ \
((C) == 'I' ? UNSIGNED_INT_FITS_N_BITS(VALUE, 3) : \
(C) == 'J' ? UNSIGNED_INT_FITS_N_BITS(VALUE, 4) : \
(C) == 'K' ? UNSIGNED_INT_FITS_N_BITS(VALUE, 5) : \
(C) == 'L' ? INT_CST4(VALUE) : \
0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' ? crx_const_double_ok (VALUE) : \
0)
/*****************************************************************************/
/* STACK LAYOUT AND CALLING CONVENTIONS. */
/*****************************************************************************/
#define STACK_GROWS_DOWNWARD
#define STARTING_FRAME_OFFSET 0
#define STACK_POINTER_REGNUM 15
#define FRAME_POINTER_REGNUM 13
#define ARG_POINTER_REGNUM 12
#define STATIC_CHAIN_REGNUM 1
#define RETURN_ADDRESS_REGNUM 14
#define FIRST_PARM_OFFSET(FNDECL) 0
#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
#define ELIMINABLE_REGS \
{ \
{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
}
#define CAN_ELIMINATE(FROM, TO) \
((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
do { \
(OFFSET) = crx_initial_elimination_offset ((FROM), (TO)); \
} while (0)
/*****************************************************************************/
/* PASSING FUNCTION ARGUMENTS */
/*****************************************************************************/
#define ACCUMULATE_OUTGOING_ARGS (TARGET_NO_PUSH_ARGS)
#define PUSH_ARGS (!TARGET_NO_PUSH_ARGS)
#define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)
#define RETURN_POPS_ARGS(FNDECL, FUNTYPE, SIZE) 0
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
((rtx) crx_function_arg(&(CUM), (MODE), (TYPE), (NAMED)))
#ifndef CUMULATIVE_ARGS
struct cumulative_args
{
int ints;
};
#define CUMULATIVE_ARGS struct cumulative_args
#endif
/* On the CRX architecture, Varargs routines should receive their parameters on
* the stack. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
crx_init_cumulative_args(&(CUM), (FNTYPE), (LIBNAME))
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
crx_function_arg_advance(&(CUM), (MODE), (TYPE), (NAMED))
#define FUNCTION_ARG_REGNO_P(REGNO) crx_function_arg_regno_p((REGNO))
/*****************************************************************************/
/* RETURNING FUNCTION VALUE */
/*****************************************************************************/
/* On the CRX, the return value is in R0 */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
gen_rtx_REG(TYPE_MODE (VALTYPE), 0)
#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
#define CRX_STRUCT_VALUE_REGNUM 0
/*****************************************************************************/
/* GENERATING CODE FOR PROFILING - NOT IMPLEMENTED */
/*****************************************************************************/
#undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(STREAM, LABELNO) \
{ \
sorry ("Profiler support for CRX"); \
}
/*****************************************************************************/
/* TRAMPOLINES FOR NESTED FUNCTIONS - NOT SUPPORTED */
/*****************************************************************************/
#define TRAMPOLINE_SIZE 32
#define INITIALIZE_TRAMPOLINE(addr, fnaddr, static_chain) \
{ \
sorry ("Trampoline support for CRX"); \
}
/*****************************************************************************/
/* ADDRESSING MODES */
/*****************************************************************************/
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF \
|| GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST \
|| GET_CODE (X) == CONST_INT)
#define MAX_REGS_PER_ADDRESS 2
#define HAVE_POST_INCREMENT 1
#define HAVE_POST_DECREMENT 1
#define HAVE_POST_MODIFY_DISP 1
#define HAVE_POST_MODIFY_REG 0
#define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#define STRICT_REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P(REGNO(X))
#define STRICT_REG_OK_FOR_INDEXED_BASE_P(X) REGNO_OK_FOR_INDEXED_BASE_P(REGNO(X))
#define NONSTRICT_REG_OK_FOR_BASE_P(X) 1
#define NONSTRICT_REG_OK_FOR_INDEX_P(X) 1
#define NONSTRICT_REG_OK_FOR_INDEXED_BASE_P(X) 1
#ifdef REG_OK_STRICT
#define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P(X)
#define REG_OK_FOR_INDEX_P(X) STRICT_REG_OK_FOR_INDEX_P(X)
#define REG_OK_FOR_INDEXED_BASE_P(X) STRICT_REG_OK_FOR_INDEXED_BASE_P(X)
#else
#define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P(X)
#define REG_OK_FOR_INDEX_P(X) NONSTRICT_REG_OK_FOR_INDEX_P(X)
#define REG_OK_FOR_INDEXED_BASE_P(X) NONSTRICT_REG_OK_FOR_INDEXED_BASE_P(X)
#endif /* REG_OK_STRICT */
#ifdef REG_OK_STRICT
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
{ \
if (crx_legitimate_address_p (MODE, X, 1)) \
goto LABEL; \
}
#else
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
{ \
if (crx_legitimate_address_p (MODE, X, 0)) \
goto LABEL; \
}
#endif
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) {}
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
{ \
if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) \
goto LABEL; \
}
#define LEGITIMATE_CONSTANT_P(X) 1
/*****************************************************************************/
/* CONDITION CODE STATUS */
/*****************************************************************************/
/*****************************************************************************/
/* RELATIVE COSTS OF OPERATIONS */
/*****************************************************************************/
#define MEMORY_MOVE_COST(MODE, CLASS, IN) crx_memory_move_cost(MODE, CLASS, IN)
/* Moving to processor register flushes pipeline - thus asymmetric */
#define REGISTER_MOVE_COST(MODE, FROM, TO) ((TO != GENERAL_REGS) ? 8 : 2)
/* Assume best case (branch predicted) */
#define BRANCH_COST 2
#define SLOW_BYTE_ACCESS 1
/*****************************************************************************/
/* DIVIDING THE OUTPUT INTO SECTIONS */
/*****************************************************************************/
#define TEXT_SECTION_ASM_OP "\t.section\t.text"
#define DATA_SECTION_ASM_OP "\t.section\t.data"
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
/*****************************************************************************/
/* POSITION INDEPENDENT CODE */
/*****************************************************************************/
#define PIC_OFFSET_TABLE_REGNUM 12
#define LEGITIMATE_PIC_OPERAND_P(X) 1
/*****************************************************************************/
/* ASSEMBLER FORMAT */
/*****************************************************************************/
#define GLOBAL_ASM_OP "\t.globl\t"
#undef USER_LABEL_PREFIX
#define USER_LABEL_PREFIX "_"
#undef ASM_OUTPUT_LABELREF
#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME));
#undef ASM_APP_ON
#define ASM_APP_ON "#APP\n"
#undef ASM_APP_OFF
#define ASM_APP_OFF "#NO_APP\n"
/*****************************************************************************/
/* INSTRUCTION OUTPUT */
/*****************************************************************************/
#define REGISTER_NAMES \
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "ra", "sp", \
"lo", "hi", "cc" \
}
#define PRINT_OPERAND(STREAM, X, CODE) \
crx_print_operand(STREAM, X, CODE)
#define PRINT_OPERAND_ADDRESS(STREAM, ADDR) \
crx_print_operand_address(STREAM, ADDR)
/*****************************************************************************/
/* OUTPUT OF DISPATCH TABLES */
/*****************************************************************************/
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
asm_fprintf ((STREAM), "\t.long\t.L%d\n", (VALUE))
/*****************************************************************************/
/* ALIGNMENT IN ASSEMBLER FILE */
/*****************************************************************************/
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
asm_fprintf ((STREAM), "\t.align\t%d\n", 1 << (POWER))
/*****************************************************************************/
/* MISCELLANEOUS PARAMETERS */
/*****************************************************************************/
#define CASE_VECTOR_MODE Pmode
#define MOVE_MAX 4
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define STORE_FLAG_VALUE 1
#define Pmode SImode
#define FUNCTION_MODE QImode
/*****************************************************************************/
/* EXTERNAL DECLARATIONS FOR VARIABLES DEFINED IN CRX.C */
/*****************************************************************************/
extern rtx crx_compare_op0; /* operand 0 for comparisons */
extern rtx crx_compare_op1; /* operand 1 for comparisons */
#endif /* ! GCC_CRX_H */

920
gcc/config/crx/crx.md Normal file
View file

@ -0,0 +1,920 @@
;; GCC machine description for CRX.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
;; 2001, 2002, 2003, 2004
;; Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA. */
;; Register numbers
(define_constants
[(SP_REGNUM 15) ; Stack pointer
(RA_REGNUM 14) ; Return address
(LO_REGNUM 16) ; LO register
(HI_REGNUM 17) ; HI register
(CC_REGNUM 18) ; Condition code register
]
)
(define_attr "length" "" ( const_int 6 ) )
(define_asm_attributes
[(set_attr "length" "6")]
)
;; Predicates
(define_predicate "u4bits_operand"
(match_code "const_int,const_double")
{
if (GET_CODE (op) == CONST_DOUBLE)
return crx_const_double_ok (op);
return (UNSIGNED_INT_FITS_N_BITS(INTVAL(op), 4)) ? 1 : 0;
}
)
(define_predicate "cst4_operand"
(and (match_code "const_int")
(match_test "INT_CST4(INTVAL(op))")))
(define_predicate "reg_or_u4bits_operand"
(ior (match_operand 0 "u4bits_operand")
(match_operand 0 "register_operand")))
(define_predicate "reg_or_cst4_operand"
(ior (match_operand 0 "cst4_operand")
(match_operand 0 "register_operand")))
(define_predicate "reg_or_sym_operand"
(ior (match_code "symbol_ref")
(match_operand 0 "register_operand")))
(define_predicate "nosp_reg_operand"
(and (match_operand 0 "register_operand")
(match_test "REGNO (op) != SP_REGNUM")))
(define_predicate "store_operand"
(and (match_operand 0 "memory_operand")
(not (match_operand 0 "push_operand"))))
;; Mode Macro Definitions
(define_mode_macro ALLMT [QI HI SI SF DI DF])
(define_mode_macro CRXMM [QI HI SI SF])
(define_mode_macro CRXIM [QI HI SI])
(define_mode_macro DIDFM [DI DF])
(define_mode_macro SISFM [SI SF])
(define_mode_macro SHORT [QI HI])
(define_mode_attr tIsa [(QI "b") (HI "w") (SI "d") (SF "d")])
(define_mode_attr lImmArith [(QI "4") (HI "4") (SI "6")])
(define_mode_attr lImmRotl [(QI "2") (HI "2") (SI "4")])
(define_mode_attr IJK [(QI "I") (HI "J") (SI "K")])
(define_mode_attr iF [(QI "i") (HI "i") (SI "i") (DI "i") (SF "F") (DF "F")])
(define_mode_attr JG [(QI "J") (HI "J") (SI "J") (DI "J") (SF "G") (DF "G")])
; In HI or QI mode we push 4 bytes.
(define_mode_attr pushCnstr [(QI "X") (HI "X") (SI "<") (SF "<") (DI "<") (DF "<")])
(define_mode_attr tpush [(QI "") (HI "") (SI "") (SF "") (DI "sp, ") (DF "sp, ")])
(define_mode_attr lpush [(QI "2") (HI "2") (SI "2") (SF "2") (DI "4") (DF "4")])
;; Code Macro Definitions
(define_code_macro sz_xtnd [sign_extend zero_extend])
(define_code_attr sIsa [(sign_extend "") (zero_extend "u")])
(define_code_attr sPat [(sign_extend "s") (zero_extend "u")])
(define_code_attr szPat [(sign_extend "") (zero_extend "zero_")])
(define_code_attr szIsa [(sign_extend "s") (zero_extend "z")])
(define_code_macro sh_oprnd [ashift ashiftrt lshiftrt])
(define_code_attr shIsa [(ashift "ll") (ashiftrt "ra") (lshiftrt "rl")])
(define_code_attr shPat [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr")])
(define_code_macro mima_oprnd [smax umax smin umin])
(define_code_attr mimaIsa [(smax "maxs") (umax "maxu") (smin "mins") (umin "minu")])
(define_code_macro any_cond [eq ne gt gtu lt ltu ge geu le leu])
;; Addition Instructions
(define_insn "adddi3"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(plus:DI (match_operand:DI 1 "register_operand" "%0,0")
(match_operand:DI 2 "nonmemory_operand" "r,i")))
(clobber (reg:CC CC_REGNUM))]
""
"addd\\t%L2, %L1\;addcd\\t%H2, %H1"
[(set_attr "length" "4,12")]
)
(define_insn "add<mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r,r")
(plus:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
(match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
(clobber (reg:CC CC_REGNUM))]
""
"add<tIsa>\\t%2, %0"
[(set_attr "length" "2,<lImmArith>")]
)
;; Subtract Instructions
(define_insn "subdi3"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "nonmemory_operand" "r,i")))
(clobber (reg:CC CC_REGNUM))]
""
"subd\\t%L2, %L1\;subcd\\t%H2, %H1"
[(set_attr "length" "4,12")]
)
(define_insn "sub<mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r,r")
(minus:CRXIM (match_operand:CRXIM 1 "register_operand" "0,0")
(match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
(clobber (reg:CC CC_REGNUM))]
""
"sub<tIsa>\\t%2, %0"
[(set_attr "length" "2,<lImmArith>")]
)
;; Multiply Instructions
(define_insn "mul<mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r,r")
(mult:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
(match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
(clobber (reg:CC CC_REGNUM))]
""
"mul<tIsa>\\t%2, %0"
[(set_attr "length" "2,<lImmArith>")]
)
;; Widening-multiplication Instructions
(define_insn "<sIsa>mulsidi3"
[(set (match_operand:DI 0 "register_operand" "=k")
(mult:DI (sz_xtnd:DI (match_operand:SI 1 "register_operand" "%r"))
(sz_xtnd:DI (match_operand:SI 2 "register_operand" "r"))))
(clobber (reg:CC CC_REGNUM))]
""
"mull<sPat>d\\t%2, %1"
[(set_attr "length" "4")]
)
(define_insn "<sIsa>mulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (sz_xtnd:SI (match_operand:HI 1 "register_operand" "%0"))
(sz_xtnd:SI (match_operand:HI 2 "register_operand" "r"))))
(clobber (reg:CC CC_REGNUM))]
""
"mul<sPat>wd\\t%2, %0"
[(set_attr "length" "4")]
)
(define_insn "<sIsa>mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(mult:HI (sz_xtnd:HI (match_operand:QI 1 "register_operand" "%0"))
(sz_xtnd:HI (match_operand:QI 2 "register_operand" "r"))))
(clobber (reg:CC CC_REGNUM))]
""
"mul<sPat>bw\\t%2, %0"
[(set_attr "length" "4")]
)
;; Logical Instructions - and
(define_insn "and<mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r,r")
(and:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
(match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
(clobber (reg:CC CC_REGNUM))]
""
"and<tIsa>\\t%2, %0"
[(set_attr "length" "2,<lImmArith>")]
)
;; Logical Instructions - or
(define_insn "ior<mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r,r")
(ior:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
(match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
(clobber (reg:CC CC_REGNUM))]
""
"or<tIsa>\\t%2, %0"
[(set_attr "length" "2,<lImmArith>")]
)
;; Logical Instructions - xor
(define_insn "xor<mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r,r")
(xor:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
(match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
(clobber (reg:CC CC_REGNUM))]
""
"xor<tIsa>\\t%2, %0"
[(set_attr "length" "2,<lImmArith>")]
)
;; Sign and Zero Extend Instructions
(define_insn "<szPat>extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(sz_xtnd:SI (match_operand:HI 1 "register_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
""
"<szIsa>extwd\\t%1, %0"
[(set_attr "length" "4")]
)
(define_insn "<szPat>extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(sz_xtnd:SI (match_operand:QI 1 "register_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
""
"<szIsa>extbd\\t%1, %0"
[(set_attr "length" "4")]
)
(define_insn "<szPat>extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=r")
(sz_xtnd:HI (match_operand:QI 1 "register_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
""
"<szIsa>extbw\\t%1, %0"
[(set_attr "length" "4")]
)
;; Negation Instructions
(define_insn "neg<mode>2"
[(set (match_operand:CRXIM 0 "register_operand" "=r")
(neg:CRXIM (match_operand:CRXIM 1 "register_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
""
"neg<tIsa>\\t%1, %0"
[(set_attr "length" "4")]
)
;; Absolute Instructions
(define_insn "abs<mode>2"
[(set (match_operand:CRXIM 0 "register_operand" "=r")
(abs:CRXIM (match_operand:CRXIM 1 "register_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
""
"abs<tIsa>\\t%1, %0"
[(set_attr "length" "4")]
)
;; Max and Min Instructions
(define_insn "<code><mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r")
(mima_oprnd:CRXIM (match_operand:CRXIM 1 "register_operand" "%0")
(match_operand:CRXIM 2 "register_operand" "r")))]
""
"<mimaIsa><tIsa>\\t%2, %0"
[(set_attr "length" "4")]
)
;; One's Complement
(define_insn "one_cmpl<mode>2"
[(set (match_operand:CRXIM 0 "register_operand" "=r")
(not:CRXIM (match_operand:CRXIM 1 "register_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
""
"xor<tIsa>\\t$-1, %0"
[(set_attr "length" "2")]
)
;; Rotate Instructions
(define_insn "rotl<mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r,r")
(rotate:CRXIM (match_operand:CRXIM 1 "register_operand" "0,0")
(match_operand:CRXIM 2 "nonmemory_operand" "r,<IJK>")))
(clobber (reg:CC CC_REGNUM))]
""
"@
rotl<tIsa>\\t%2, %0
rot<tIsa>\\t%2, %0"
[(set_attr "length" "4,<lImmRotl>")]
)
(define_insn "rotr<mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r")
(rotatert:CRXIM (match_operand:CRXIM 1 "register_operand" "0")
(match_operand:CRXIM 2 "register_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
""
"rotr<tIsa>\\t%2, %0"
[(set_attr "length" "4")]
)
;; Arithmetic Left and Right Shift Instructions
(define_insn "<shPat><mode>3"
[(set (match_operand:CRXIM 0 "register_operand" "=r,r")
(sh_oprnd:CRXIM (match_operand:CRXIM 1 "register_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "r,<IJK>")))
(clobber (reg:CC CC_REGNUM))]
""
"s<shIsa><tIsa>\\t%2, %0"
[(set_attr "length" "2,2")]
)
;; Bit Set Instructions
(define_insn "extv"
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
""
{
static char buf[100];
int strpntr;
int size = INTVAL (operands[2]);
int pos = INTVAL (operands[3]);
strpntr = sprintf (buf, "ram\t$%d, $31, $%d, %%1, %%0\;",
BITS_PER_WORD - (size + pos), BITS_PER_WORD - size);
sprintf (buf + strpntr, "srad\t$%d, %%0", BITS_PER_WORD - size);
return buf;
}
[(set_attr "length" "6")]
)
(define_insn "extzv"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
""
{
static char buf[40];
int size = INTVAL (operands[2]);
int pos = INTVAL (operands[3]);
sprintf (buf, "ram\t$%d, $%d, $0, %%1, %%0",
(BITS_PER_WORD - pos) % BITS_PER_WORD, size - 1);
return buf;
}
[(set_attr "length" "4")]
)
(define_insn "insv"
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))
(match_operand:SI 3 "register_operand" "r"))]
""
{
static char buf[40];
int size = INTVAL (operands[1]);
int pos = INTVAL (operands[2]);
sprintf (buf, "rim\t$%d, $%d, $%d, %%3, %%0",
pos, size + pos - 1, pos);
return buf;
}
[(set_attr "length" "4")]
)
;; Move Instructions
(define_expand "mov<mode>"
[(set (match_operand:ALLMT 0 "nonimmediate_operand" "")
(match_operand:ALLMT 1 "general_operand" ""))]
""
{
if (!(reload_in_progress || reload_completed))
{
if (!register_operand (operands[0], <MODE>mode))
{
if (push_operand (operands[0], <MODE>mode) ?
!nosp_reg_operand (operands[1], <MODE>mode) :
!reg_or_u4bits_operand (operands[1], <MODE>mode))
{
operands[1] = copy_to_mode_reg (<MODE>mode, operands[1]);
}
}
}
}
)
(define_insn "push<mode>_internal"
[(set (match_operand:ALLMT 0 "push_operand" "=<pushCnstr>")
(match_operand:ALLMT 1 "nosp_reg_operand" "b"))]
""
"push\t<tpush>%p1"
[(set_attr "length" "<lpush>")]
)
(define_insn "mov<mode>_regs"
[(set (match_operand:SISFM 0 "register_operand" "=r, r, r, k")
(match_operand:SISFM 1 "nonmemory_operand" "r, <iF>, k, r"))]
""
"@
movd\\t%1, %0
movd\\t%1, %0
mfpr\\t%1, %0
mtpr\\t%1, %0"
[(set_attr "length" "2,6,4,4")]
)
(define_insn "mov<mode>_regs"
[(set (match_operand:DIDFM 0 "register_operand" "=r, r, r, k")
(match_operand:DIDFM 1 "nonmemory_operand" "r, <iF>, k, r"))]
""
{
switch (which_alternative)
{
case 0: if (REGNO (operands[0]) > REGNO (operands[1]))
return "movd\t%H1, %H0\;movd\t%L1, %L0";
else
return "movd\t%L1, %L0\;movd\t%H1, %H0";
case 1: return "movd\t%H1, %H0\;movd\t%L1, %L0";
case 2: return "mfpr\t%H1, %H0\;mfpr\t%L1, %L0";
case 3: return "mtpr\t%H1, %H0\;mtpr\t%L1, %L0";
default: gcc_unreachable ();
}
}
[(set_attr "length" "4,12,8,8")]
)
(define_insn "mov<mode>_regs" ; no HI/QI mode in HILO regs
[(set (match_operand:SHORT 0 "register_operand" "=r, r")
(match_operand:SHORT 1 "nonmemory_operand" "r, i"))]
""
"mov<tIsa>\\t%1, %0"
[(set_attr "length" "2,<lImmArith>")]
)
(define_insn "mov<mode>_load"
[(set (match_operand:CRXMM 0 "register_operand" "=r")
(match_operand:CRXMM 1 "memory_operand" "m"))]
""
"load<tIsa>\\t%1, %0"
[(set_attr "length" "6")]
)
(define_insn "mov<mode>_load"
[(set (match_operand:DIDFM 0 "register_operand" "=r")
(match_operand:DIDFM 1 "memory_operand" "m"))]
""
{
rtx first_dest_reg = gen_rtx_REG (SImode, REGNO (operands[0]));
if (reg_overlap_mentioned_p (first_dest_reg, operands[1]))
return "loadd\t%H1, %H0\;loadd\t%L1, %L0";
return "loadd\t%L1, %L0\;loadd\t%H1, %H0";
}
[(set_attr "length" "12")]
)
(define_insn "mov<mode>_store"
[(set (match_operand:CRXMM 0 "store_operand" "=m, m")
(match_operand:CRXMM 1 "reg_or_u4bits_operand" "r, <JG>"))]
""
"stor<tIsa>\\t%1, %0"
[(set_attr "length" "6")]
)
(define_insn "mov<mode>_store"
[(set (match_operand:DIDFM 0 "store_operand" "=m, m")
(match_operand:DIDFM 1 "reg_or_u4bits_operand" "r, <JG>"))]
""
"stord\t%H1, %H0\;stord\t%L1, %L0"
[(set_attr "length" "12")]
)
;; Movmem Instruction
(define_expand "movmemsi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:BLK 1 "memory_operand" ""))
(use (match_operand:SI 2 "nonmemory_operand" ""))
(use (match_operand:SI 3 "const_int_operand" ""))]
""
{
if (crx_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
}
)
;; Compare and Branch Instructions
(define_insn "cbranch<mode>4"
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(match_operand:CRXIM 1 "register_operand" "r")
(match_operand:CRXIM 2 "reg_or_cst4_operand" "rL")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
"cmpb%d0<tIsa>\\t%2, %1, %l3"
[(set_attr "length" "6")]
)
;; Compare Instructions
(define_expand "cmp<mode>"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:CRXIM 0 "register_operand" "")
(match_operand:CRXIM 1 "nonmemory_operand" "")))]
""
{
crx_compare_op0 = operands[0];
crx_compare_op1 = operands[1];
DONE;
}
)
(define_insn "cmp<mode>_internal"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:CRXIM 0 "register_operand" "r,r")
(match_operand:CRXIM 1 "nonmemory_operand" "r,i")))]
""
"cmp<tIsa>\\t%1, %0"
[(set_attr "length" "2,<lImmArith>")]
)
;; Conditional Branch Instructions
(define_expand "b<code>"
[(set (pc)
(if_then_else (any_cond (reg:CC CC_REGNUM)
(const_int 0))
(label_ref (match_operand 0 ""))
(pc)))]
""
{
crx_expand_branch (<CODE>, operands[0]);
DONE;
}
)
(define_insn "bCOND_internal"
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(reg:CC CC_REGNUM)
(const_int 0)])
(label_ref (match_operand 1 ""))
(pc)))]
""
"b%d0\\t%l1"
[(set_attr "length" "6")]
)
;; Scond Instructions
(define_expand "s<code>"
[(set (match_operand:SI 0 "register_operand")
(any_cond:SI (reg:CC CC_REGNUM) (const_int 0)))]
""
{
crx_expand_scond (<CODE>, operands[0]);
DONE;
}
)
(define_insn "sCOND_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operator:SI 1 "comparison_operator"
[(reg:CC CC_REGNUM) (const_int 0)]))]
""
"s%d1\\t%0"
[(set_attr "length" "2")]
)
;; Jumps and Branches
(define_insn "indirect_jump_return"
[(parallel
[(set (pc)
(reg:SI RA_REGNUM))
(return)])
]
"reload_completed"
"jump\\tra"
[(set_attr "length" "2")]
)
(define_insn "indirect_jump"
[(set (pc)
(match_operand:SI 0 "reg_or_sym_operand" "r,i"))]
""
"@
jump\\t%0
br\\t%a0"
[(set_attr "length" "2,6")]
)
(define_insn "interrupt_return"
[(parallel
[(unspec_volatile [(const_int 0)] 0)
(return)])]
""
{
return crx_prepare_push_pop_string (1);
}
[(set_attr "length" "14")]
)
(define_insn "jump_to_imm"
[(set (pc)
(match_operand 0 "immediate_operand" "i"))]
""
"br\\t%c0"
[(set_attr "length" "6")]
)
(define_insn "jump"
[(set (pc)
(label_ref (match_operand 0 "" "")))]
""
"br\\t%l0"
[(set_attr "length" "6")]
)
;; Function Prologue and Epilogue
(define_expand "prologue"
[(const_int 0)]
""
{
crx_expand_prologue ();
DONE;
}
)
(define_insn "push_for_prologue"
[(parallel
[(set (reg:SI SP_REGNUM)
(minus:SI (reg:SI SP_REGNUM)
(match_operand:SI 0 "immediate_operand" "i")))])]
"reload_completed"
{
return crx_prepare_push_pop_string (0);
}
[(set_attr "length" "4")]
)
(define_expand "epilogue"
[(return)]
""
{
crx_expand_epilogue ();
DONE;
}
)
(define_insn "pop_and_popret_return"
[(parallel
[(set (reg:SI SP_REGNUM)
(plus:SI (reg:SI SP_REGNUM)
(match_operand:SI 0 "immediate_operand" "i")))
(use (reg:SI RA_REGNUM))
(return)])
]
"reload_completed"
{
return crx_prepare_push_pop_string (1);
}
[(set_attr "length" "4")]
)
(define_insn "popret_RA_return"
[(parallel
[(use (reg:SI RA_REGNUM))
(return)])
]
"reload_completed"
"popret\\tra"
[(set_attr "length" "2")]
)
;; Table Jump
(define_insn "tablejump"
[(set (pc)
(match_operand:SI 0 "register_operand" "r"))
(use (label_ref:SI (match_operand 1 "" "" )))]
""
"jump\\t%0"
[(set_attr "length" "2")]
)
;; Call Instructions
(define_expand "call"
[(call (match_operand:QI 0 "memory_operand" "")
(match_operand 1 "" ""))]
""
{
emit_call_insn (gen_crx_call (operands[0], operands[1]));
DONE;
}
)
(define_expand "crx_call"
[(parallel
[(call (match_operand:QI 0 "memory_operand" "")
(match_operand 1 "" ""))
(clobber (reg:SI RA_REGNUM))])]
""
""
)
(define_insn "crx_call_insn_branch"
[(call (mem:QI (match_operand:SI 0 "immediate_operand" "i"))
(match_operand 1 "" ""))
(clobber (match_operand:SI 2 "register_operand" "+r"))]
""
"bal\\tra, %a0"
[(set_attr "length" "6")]
)
(define_insn "crx_call_insn_jump"
[(call (mem:QI (match_operand:SI 0 "register_operand" "r"))
(match_operand 1 "" ""))
(clobber (match_operand:SI 2 "register_operand" "+r"))]
""
"jal\\t%0"
[(set_attr "length" "2")]
)
(define_insn "crx_call_insn_jalid"
[(call (mem:QI (mem:SI (plus:SI
(match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "register_operand" "r"))))
(match_operand 2 "" ""))
(clobber (match_operand:SI 3 "register_operand" "+r"))]
""
"jalid\\t%0, %1"
[(set_attr "length" "4")]
)
;; Call Value Instructions
(define_expand "call_value"
[(set (match_operand 0 "general_operand" "")
(call (match_operand:QI 1 "memory_operand" "")
(match_operand 2 "" "")))]
""
{
emit_call_insn (gen_crx_call_value (operands[0], operands[1], operands[2]));
DONE;
}
)
(define_expand "crx_call_value"
[(parallel
[(set (match_operand 0 "general_operand" "")
(call (match_operand 1 "memory_operand" "")
(match_operand 2 "" "")))
(clobber (reg:SI RA_REGNUM))])]
""
""
)
(define_insn "crx_call_value_insn_branch"
[(set (match_operand 0 "" "=g")
(call (mem:QI (match_operand:SI 1 "immediate_operand" "i"))
(match_operand 2 "" "")))
(clobber (match_operand:SI 3 "register_operand" "+r"))]
""
"bal\\tra, %a1"
[(set_attr "length" "6")]
)
(define_insn "crx_call_value_insn_jump"
[(set (match_operand 0 "" "=g")
(call (mem:QI (match_operand:SI 1 "register_operand" "r"))
(match_operand 2 "" "")))
(clobber (match_operand:SI 3 "register_operand" "+r"))]
""
"jal\\t%1"
[(set_attr "length" "2")]
)
(define_insn "crx_call_value_insn_jalid"
[(set (match_operand 0 "" "=g")
(call (mem:QI (mem:SI (plus:SI
(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r"))))
(match_operand 3 "" "")))
(clobber (match_operand:SI 4 "register_operand" "+r"))]
""
"jalid\\t%0, %1"
[(set_attr "length" "4")]
)
;; Nop
(define_insn "nop"
[(const_int 0)]
""
""
)
;; Multiply and Accumulate Instructions
(define_insn "<sPat>madsidi3"
[(set (match_operand:DI 0 "register_operand" "+k")
(plus:DI
(mult:DI (sz_xtnd:DI (match_operand:SI 1 "register_operand" "%r"))
(sz_xtnd:DI (match_operand:SI 2 "register_operand" "r")))
(match_dup 0)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_MAC"
"mac<sPat>d\\t%2, %1"
[(set_attr "length" "4")]
)
(define_insn "<sPat>madhisi3"
[(set (match_operand:SI 0 "register_operand" "+l")
(plus:SI
(mult:SI (sz_xtnd:SI (match_operand:HI 1 "register_operand" "%r"))
(sz_xtnd:SI (match_operand:HI 2 "register_operand" "r")))
(match_dup 0)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_MAC"
"mac<sPat>w\\t%2, %1"
[(set_attr "length" "4")]
)
(define_insn "<sPat>madqihi3"
[(set (match_operand:HI 0 "register_operand" "+l")
(plus:HI
(mult:HI (sz_xtnd:HI (match_operand:QI 1 "register_operand" "%r"))
(sz_xtnd:HI (match_operand:QI 2 "register_operand" "r")))
(match_dup 0)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_MAC"
"mac<sPat>b\\t%2, %1"
[(set_attr "length" "4")]
)
;; Loop Instructions
(define_expand "doloop_end"
[(use (match_operand 0 "" "")) ; loop pseudo
(use (match_operand 1 "" "")) ; iterations; zero if unknown
(use (match_operand 2 "" "")) ; max iterations
(use (match_operand 3 "" "")) ; loop level
(use (match_operand 4 "" ""))] ; label
""
{
switch (GET_MODE (operands[0]))
{
case SImode:
emit_jump_insn (gen_doloop_end_si (operands[4], operands[0], operands[0]));
break;
case HImode:
emit_jump_insn (gen_doloop_end_hi (operands[4], operands[0], operands[0]));
break;
case QImode:
emit_jump_insn (gen_doloop_end_qi (operands[4], operands[0], operands[0]));
break;
default:
FAIL;
}
DONE;
}
)
(define_insn "doloop_end_<mode>"
[(set (pc)
(if_then_else (ne (match_operand:CRXIM 1 "register_operand" "r,m")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
(set (match_operand:CRXIM 2 "register_operand" "=r,m") (plus:CRXIM (match_dup 1) (const_int -1)))
(clobber (match_scratch:CRXIM 3 "=X,r"))
(clobber (reg:CC CC_REGNUM))]
""
"@
dbnz<tIsa>\\t%1, %l0
load<tIsa>\\t%1, %3\;add<tIsa>\\t$-1, %3\;stor<tIsa>\\t%3, %1\;bne\\t%l0"
[(set_attr "length" "6, 12")]
)

28
gcc/config/crx/crx.opt Normal file
View file

@ -0,0 +1,28 @@
; Options for the National Semiconductor CRX port of the compiler.
; Copyright (C) 2005 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 2, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING. If not, write to the Free
; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
; 02110-1301, USA.
mmac
Target Report Mask(MAC)
Support multiply accumulate instructions
mno-push-args
Target Report RejectNegative Mask(NO_PUSH_ARGS)
Do not use push to store function arguments

19
gcc/config/crx/t-crx Normal file
View file

@ -0,0 +1,19 @@
# CRX Target Makefile
# Mingw specific compilation fixes
USE_COLLECT2 =
STMP_FIXINC =
# Software emulation for integer div and mod
LIB2FUNCS_EXTRA = $(srcdir)/config/udivmodsi4.c $(srcdir)/config/udivmod.c $(srcdir)/config/divmod.c
# Build the floating point emulation libraries.
FPBIT = fp-bit.c
DPBIT = dp-bit.c
fp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define FLOAT' > fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
dp-bit.c: $(srcdir)/config/fp-bit.c
cat $(srcdir)/config/fp-bit.c > dp-bit.c