[ARM/AArch64][testsuite] Add vsli_n and vsri_n tests.
2015-01-21 Christophe Lyon <christophe.lyon@linaro.org> * gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vsri_n.c: New file. From-SVN: r219934
This commit is contained in:
Christophe Lyon
Christophe Lyon
parent
c18b73e1d0
commit
d9355320f1
4 changed files with 414 additions and 0 deletions
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2015-01-21 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc: New file.
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* gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: New file.
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* gcc.target/aarch64/advsimd-intrinsics/vsri_n.c: New file.
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2015-01-21 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc: New file.
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#define FNNAME1(NAME) exec_ ## NAME ##_n
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#define FNNAME(NAME) FNNAME1(NAME)
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void FNNAME (INSN_NAME) (void)
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{
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/* vector_res = vsxi_n(vector, vector2, val),
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then store the result. */
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#define TEST_VSXI_N1(INSN, Q, T1, T2, W, N, V) \
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VECT_VAR(vector_res, T1, W, N) = \
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INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
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VECT_VAR(vector2, T1, W, N), \
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V); \
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vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
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#define TEST_VSXI_N(INSN, Q, T1, T2, W, N, V) \
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TEST_VSXI_N1(INSN, Q, T1, T2, W, N, V)
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DECL_VARIABLE_ALL_VARIANTS(vector);
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DECL_VARIABLE_ALL_VARIANTS(vector2);
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DECL_VARIABLE_ALL_VARIANTS(vector_res);
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clean_results ();
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/* Initialize input "vector" from "buffer". */
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TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
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/* Fill input vector2 with arbitrary values. */
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VDUP(vector2, , int, s, 8, 8, 2);
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VDUP(vector2, , int, s, 16, 4, -4);
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VDUP(vector2, , int, s, 32, 2, 3);
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VDUP(vector2, , int, s, 64, 1, 100);
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VDUP(vector2, , uint, u, 8, 8, 20);
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VDUP(vector2, , uint, u, 16, 4, 30);
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VDUP(vector2, , uint, u, 32, 2, 40);
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VDUP(vector2, , uint, u, 64, 1, 2);
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VDUP(vector2, , poly, p, 8, 8, 20);
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VDUP(vector2, , poly, p, 16, 4, 30);
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VDUP(vector2, q, int, s, 8, 16, -10);
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VDUP(vector2, q, int, s, 16, 8, -20);
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VDUP(vector2, q, int, s, 32, 4, -30);
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VDUP(vector2, q, int, s, 64, 2, 24);
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VDUP(vector2, q, uint, u, 8, 16, 12);
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VDUP(vector2, q, uint, u, 16, 8, 3);
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VDUP(vector2, q, uint, u, 32, 4, 55);
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VDUP(vector2, q, uint, u, 64, 2, 3);
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VDUP(vector2, q, poly, p, 8, 16, 12);
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VDUP(vector2, q, poly, p, 16, 8, 3);
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/* Choose shift amount arbitrarily. */
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TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 4);
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TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 3);
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TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 1);
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TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 32);
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TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 2);
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TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 10);
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TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 30);
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TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 3);
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TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 2);
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TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 10);
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TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 5);
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TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 3);
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TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 20);
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TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 16);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 3);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 12);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 23);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 53);
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TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 3);
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TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 12);
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CHECK_RESULTS (TEST_MSG, "");
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#ifdef EXTRA_TESTS
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EXTRA_TESTS();
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#endif
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}
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int main (void)
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{
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FNNAME (INSN_NAME) ();
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return 0;
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}
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162
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
Normal file
162
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
Normal file
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#include <arm_neon.h>
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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#define INSN_NAME vsli
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#define TEST_MSG "VSLI_N"
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/* Extra tests for functions requiring corner cases tests. */
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void vsli_extra(void);
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#define EXTRA_TESTS vsli_extra
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/* Expected results. */
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VECT_VAR_DECL(expected,int,8,8) [] = { 0x20, 0x21, 0x22, 0x23,
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0x24, 0x25, 0x26, 0x27 };
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VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe0, 0xffe1, 0xffe2, 0xffe3 };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0x6, 0x7 };
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VECT_VAR_DECL(expected,int,64,1) [] = { 0x64fffffff0 };
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VECT_VAR_DECL(expected,uint,8,8) [] = { 0x50, 0x51, 0x52, 0x53,
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0x50, 0x51, 0x52, 0x53 };
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VECT_VAR_DECL(expected,uint,16,4) [] = { 0x7bf0, 0x7bf1, 0x7bf2, 0x7bf3 };
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VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3ffffff0, 0x3ffffff1 };
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VECT_VAR_DECL(expected,uint,64,1) [] = { 0x10 };
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VECT_VAR_DECL(expected,poly,8,8) [] = { 0x50, 0x51, 0x52, 0x53,
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0x50, 0x51, 0x52, 0x53 };
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VECT_VAR_DECL(expected,poly,16,4) [] = { 0x7bf0, 0x7bf1, 0x7bf2, 0x7bf3 };
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VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,8,16) [] = { 0xd0, 0xd1, 0xd2, 0xd3,
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0xd4, 0xd5, 0xd6, 0xd7,
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0xd8, 0xd9, 0xda, 0xdb,
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0xdc, 0xdd, 0xde, 0xdf };
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VECT_VAR_DECL(expected,int,16,8) [] = { 0xff60, 0xff61, 0xff62, 0xff63,
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0xff64, 0xff65, 0xff66, 0xff67 };
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VECT_VAR_DECL(expected,int,32,4) [] = { 0xfe2ffff0, 0xfe2ffff1,
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0xfe2ffff2, 0xfe2ffff3 };
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VECT_VAR_DECL(expected,int,64,2) [] = { 0x18fff0, 0x18fff1 };
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VECT_VAR_DECL(expected,uint,8,16) [] = { 0x60, 0x61, 0x62, 0x63,
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0x64, 0x65, 0x66, 0x67,
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0x60, 0x61, 0x62, 0x63,
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0x64, 0x65, 0x66, 0x67 };
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VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3ff0, 0x3ff1, 0x3ff2, 0x3ff3,
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0x3ff4, 0x3ff5, 0x3ff6, 0x3ff7 };
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VECT_VAR_DECL(expected,uint,32,4) [] = { 0x1bfffff0, 0x1bfffff1,
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0x1bfffff2, 0x1bfffff3 };
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VECT_VAR_DECL(expected,uint,64,2) [] = { 0x7ffffffffffff0, 0x7ffffffffffff1 };
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VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0x61, 0x62, 0x63,
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0x64, 0x65, 0x66, 0x67,
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0x60, 0x61, 0x62, 0x63,
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0x64, 0x65, 0x66, 0x67 };
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VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3ff0, 0x3ff1, 0x3ff2, 0x3ff3,
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0x3ff4, 0x3ff5, 0x3ff6, 0x3ff7 };
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
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0x33333333, 0x33333333 };
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/* Expected results with max shift amount. */
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VECT_VAR_DECL(expected_max_shift,int,8,8) [] = { 0x70, 0x71, 0x72, 0x73,
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0x74, 0x75, 0x76, 0x77 };
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VECT_VAR_DECL(expected_max_shift,int,16,4) [] = { 0x7ff0, 0x7ff1,
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0x7ff2, 0x7ff3 };
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VECT_VAR_DECL(expected_max_shift,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
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VECT_VAR_DECL(expected_max_shift,int,64,1) [] = { 0x7ffffffffffffff0 };
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VECT_VAR_DECL(expected_max_shift,uint,8,8) [] = { 0x70, 0x71, 0x72, 0x73,
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0x74, 0x75, 0x76, 0x77 };
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VECT_VAR_DECL(expected_max_shift,uint,16,4) [] = { 0x7ff0, 0x7ff1,
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0x7ff2, 0x7ff3 };
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VECT_VAR_DECL(expected_max_shift,uint,32,2) [] = { 0x7ffffff0, 0x7ffffff1 };
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VECT_VAR_DECL(expected_max_shift,uint,64,1) [] = { 0x7ffffffffffffff0 };
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VECT_VAR_DECL(expected_max_shift,poly,8,8) [] = { 0x70, 0x71, 0x72, 0x73,
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0x74, 0x75, 0x76, 0x77 };
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VECT_VAR_DECL(expected_max_shift,poly,16,4) [] = { 0x7ff0, 0x7ff1,
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0x7ff2, 0x7ff3 };
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VECT_VAR_DECL(expected_max_shift,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected_max_shift,int,8,16) [] = { 0x70, 0x71, 0x72, 0x73,
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0x74, 0x75, 0x76, 0x77,
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0x78, 0x79, 0x7a, 0x7b,
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0x7c, 0x7d, 0x7e, 0x7f };
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VECT_VAR_DECL(expected_max_shift,int,16,8) [] = { 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3,
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0x7ff4, 0x7ff5, 0x7ff6, 0x7ff7 };
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VECT_VAR_DECL(expected_max_shift,int,32,4) [] = { 0x7ffffff0, 0x7ffffff1,
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0x7ffffff2, 0x7ffffff3 };
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VECT_VAR_DECL(expected_max_shift,int,64,2) [] = { 0x7ffffffffffffff0,
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0x7ffffffffffffff1 };
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VECT_VAR_DECL(expected_max_shift,uint,8,16) [] = { 0x70, 0x71, 0x72, 0x73,
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0x74, 0x75, 0x76, 0x77,
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0x78, 0x79, 0x7a, 0x7b,
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0x7c, 0x7d, 0x7e, 0x7f };
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VECT_VAR_DECL(expected_max_shift,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
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0xfff4, 0xfff5, 0xfff6, 0xfff7 };
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VECT_VAR_DECL(expected_max_shift,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
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0xfffffff2, 0xfffffff3 };
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VECT_VAR_DECL(expected_max_shift,uint,64,2) [] = { 0xfffffffffffffff0,
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0xfffffffffffffff1 };
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VECT_VAR_DECL(expected_max_shift,poly,8,16) [] = { 0x70, 0x71, 0x72, 0x73,
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0x74, 0x75, 0x76, 0x77,
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0x78, 0x79, 0x7a, 0x7b,
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0x7c, 0x7d, 0x7e, 0x7f };
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VECT_VAR_DECL(expected_max_shift,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
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0xfff4, 0xfff5, 0xfff6, 0xfff7 };
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VECT_VAR_DECL(expected_max_shift,hfloat,32,4) [] = { 0x33333333, 0x33333333,
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0x33333333, 0x33333333 };
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#include "vsXi_n.inc"
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void vsli_extra(void)
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{
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/* Test cases with maximum shift amount (this amount is different
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from vsri). */
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DECL_VARIABLE_ALL_VARIANTS(vector);
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DECL_VARIABLE_ALL_VARIANTS(vector2);
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DECL_VARIABLE_ALL_VARIANTS(vector_res);
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clean_results ();
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/* Initialize input "vector" from "buffer". */
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TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
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/* Fill input vector2 with arbitrary values. */
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VDUP(vector2, , int, s, 8, 8, 2);
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VDUP(vector2, , int, s, 16, 4, -4);
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VDUP(vector2, , int, s, 32, 2, 3);
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VDUP(vector2, , int, s, 64, 1, 100);
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VDUP(vector2, , uint, u, 8, 8, 20);
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VDUP(vector2, , uint, u, 16, 4, 30);
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VDUP(vector2, , uint, u, 32, 2, 40);
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VDUP(vector2, , uint, u, 64, 1, 2);
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VDUP(vector2, , poly, p, 8, 8, 20);
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VDUP(vector2, , poly, p, 16, 4, 30);
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VDUP(vector2, q, int, s, 8, 16, -10);
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VDUP(vector2, q, int, s, 16, 8, -20);
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VDUP(vector2, q, int, s, 32, 4, -30);
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VDUP(vector2, q, int, s, 64, 2, 24);
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VDUP(vector2, q, uint, u, 8, 16, 12);
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VDUP(vector2, q, uint, u, 16, 8, 3);
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VDUP(vector2, q, uint, u, 32, 4, 55);
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VDUP(vector2, q, uint, u, 64, 2, 3);
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VDUP(vector2, q, poly, p, 8, 16, 12);
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VDUP(vector2, q, poly, p, 16, 8, 3);
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/* Use maximum allowed shift amount. */
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TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 7);
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TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 15);
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TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 31);
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TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 63);
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TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 7);
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TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 15);
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TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 31);
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TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 63);
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TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 7);
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TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 15);
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TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 7);
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TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 15);
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TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 31);
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TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 63);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 7);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 15);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 31);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 63);
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TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 7);
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TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 15);
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CHECK_RESULTS_NAMED (TEST_MSG, expected_max_shift, "(max shift amount)");
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}
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164
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
Normal file
164
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
Normal file
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#include <arm_neon.h>
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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#define INSN_NAME vsri
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#define TEST_MSG "VSRI_N"
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/* Extra tests for functions requiring corner cases tests. */
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void vsri_extra(void);
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#define EXTRA_TESTS vsri_extra
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/* Expected results. */
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VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
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0xf0, 0xf0, 0xf0, 0xf0 };
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VECT_VAR_DECL(expected,int,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0x80000001, 0x80000001 };
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VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffff00000000 };
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VECT_VAR_DECL(expected,uint,8,8) [] = { 0xc5, 0xc5, 0xc5, 0xc5,
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0xc5, 0xc5, 0xc5, 0xc5 };
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VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffc0, 0xffc0, 0xffc0, 0xffc0 };
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VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
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VECT_VAR_DECL(expected,uint,64,1) [] = { 0xe000000000000000 };
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VECT_VAR_DECL(expected,poly,8,8) [] = { 0xc5, 0xc5, 0xc5, 0xc5,
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0xc5, 0xc5, 0xc5, 0xc5 };
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VECT_VAR_DECL(expected,poly,16,4) [] = { 0xffc0, 0xffc0, 0xffc0, 0xffc0 };
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VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,8,16) [] = { 0xf7, 0xf7, 0xf7, 0xf7,
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0xf7, 0xf7, 0xf7, 0xf7,
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0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff };
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VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffd, 0xfffd, 0xfffd,
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0xfffd, 0xfffd, 0xfffd, 0xfffd };
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VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff,
|
||||
0xffffffff, 0xffffffff };
|
||||
VECT_VAR_DECL(expected,int,64,2) [] = { 0xffff000000000000,
|
||||
0xffff000000000000 };
|
||||
VECT_VAR_DECL(expected,uint,8,16) [] = { 0xe1, 0xe1, 0xe1, 0xe1,
|
||||
0xe1, 0xe1, 0xe1, 0xe1,
|
||||
0xe1, 0xe1, 0xe1, 0xe1,
|
||||
0xe1, 0xe1, 0xe1, 0xe1 };
|
||||
VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
|
||||
0xfff0, 0xfff0, 0xfff0, 0xfff0 };
|
||||
VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffe00, 0xfffffe00,
|
||||
0xfffffe00, 0xfffffe00 };
|
||||
VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffff800,
|
||||
0xfffffffffffff800 };
|
||||
VECT_VAR_DECL(expected,poly,8,16) [] = { 0xe1, 0xe1, 0xe1, 0xe1,
|
||||
0xe1, 0xe1, 0xe1, 0xe1,
|
||||
0xe1, 0xe1, 0xe1, 0xe1,
|
||||
0xe1, 0xe1, 0xe1, 0xe1 };
|
||||
VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
|
||||
0xfff0, 0xfff0, 0xfff0, 0xfff0 };
|
||||
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
|
||||
0x33333333, 0x33333333 };
|
||||
|
||||
/* Expected results with max shift amount. */
|
||||
VECT_VAR_DECL(expected_max_shift,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
|
||||
0xf4, 0xf5, 0xf6, 0xf7 };
|
||||
VECT_VAR_DECL(expected_max_shift,int,16,4) [] = { 0xfff0, 0xfff1,
|
||||
0xfff2, 0xfff3 };
|
||||
VECT_VAR_DECL(expected_max_shift,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
|
||||
VECT_VAR_DECL(expected_max_shift,int,64,1) [] = { 0xfffffffffffffff0 };
|
||||
VECT_VAR_DECL(expected_max_shift,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
|
||||
0xf4, 0xf5, 0xf6, 0xf7 };
|
||||
VECT_VAR_DECL(expected_max_shift,uint,16,4) [] = { 0xfff0, 0xfff1,
|
||||
0xfff2, 0xfff3 };
|
||||
VECT_VAR_DECL(expected_max_shift,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
|
||||
VECT_VAR_DECL(expected_max_shift,uint,64,1) [] = { 0xfffffffffffffff0 };
|
||||
VECT_VAR_DECL(expected_max_shift,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
|
||||
0xf4, 0xf5, 0xf6, 0xf7 };
|
||||
VECT_VAR_DECL(expected_max_shift,poly,16,4) [] = { 0xfff0, 0xfff1,
|
||||
0xfff2, 0xfff3 };
|
||||
VECT_VAR_DECL(expected_max_shift,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
|
||||
VECT_VAR_DECL(expected_max_shift,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
|
||||
0xf4, 0xf5, 0xf6, 0xf7,
|
||||
0xf8, 0xf9, 0xfa, 0xfb,
|
||||
0xfc, 0xfd, 0xfe, 0xff };
|
||||
VECT_VAR_DECL(expected_max_shift,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
|
||||
0xfff4, 0xfff5, 0xfff6, 0xfff7 };
|
||||
VECT_VAR_DECL(expected_max_shift,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
|
||||
0xfffffff2, 0xfffffff3 };
|
||||
VECT_VAR_DECL(expected_max_shift,int,64,2) [] = { 0xfffffffffffffff0,
|
||||
0xfffffffffffffff1 };
|
||||
VECT_VAR_DECL(expected_max_shift,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
|
||||
0xf4, 0xf5, 0xf6, 0xf7,
|
||||
0xf8, 0xf9, 0xfa, 0xfb,
|
||||
0xfc, 0xfd, 0xfe, 0xff };
|
||||
VECT_VAR_DECL(expected_max_shift,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
|
||||
0xfff4, 0xfff5, 0xfff6, 0xfff7 };
|
||||
VECT_VAR_DECL(expected_max_shift,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
|
||||
0xfffffff2, 0xfffffff3 };
|
||||
VECT_VAR_DECL(expected_max_shift,uint,64,2) [] = { 0xfffffffffffffff0,
|
||||
0xfffffffffffffff1 };
|
||||
VECT_VAR_DECL(expected_max_shift,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
|
||||
0xf4, 0xf5, 0xf6, 0xf7,
|
||||
0xf8, 0xf9, 0xfa, 0xfb,
|
||||
0xfc, 0xfd, 0xfe, 0xff };
|
||||
VECT_VAR_DECL(expected_max_shift,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
|
||||
0xfff4, 0xfff5, 0xfff6, 0xfff7 };
|
||||
VECT_VAR_DECL(expected_max_shift,hfloat,32,4) [] = { 0x33333333, 0x33333333,
|
||||
0x33333333, 0x33333333 };
|
||||
|
||||
#include "vsXi_n.inc"
|
||||
|
||||
void vsri_extra(void)
|
||||
{
|
||||
/* Test cases with maximum shift amount (this amount is different
|
||||
from vsli). */
|
||||
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector);
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector2);
|
||||
DECL_VARIABLE_ALL_VARIANTS(vector_res);
|
||||
|
||||
clean_results ();
|
||||
|
||||
/* Initialize input "vector" from "buffer". */
|
||||
TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
|
||||
|
||||
/* Fill input vector2 with arbitrary values. */
|
||||
VDUP(vector2, , int, s, 8, 8, 2);
|
||||
VDUP(vector2, , int, s, 16, 4, -4);
|
||||
VDUP(vector2, , int, s, 32, 2, 3);
|
||||
VDUP(vector2, , int, s, 64, 1, 100);
|
||||
VDUP(vector2, , uint, u, 8, 8, 20);
|
||||
VDUP(vector2, , uint, u, 16, 4, 30);
|
||||
VDUP(vector2, , uint, u, 32, 2, 40);
|
||||
VDUP(vector2, , uint, u, 64, 1, 2);
|
||||
VDUP(vector2, , poly, p, 8, 8, 20);
|
||||
VDUP(vector2, , poly, p, 16, 4, 30);
|
||||
VDUP(vector2, q, int, s, 8, 16, -10);
|
||||
VDUP(vector2, q, int, s, 16, 8, -20);
|
||||
VDUP(vector2, q, int, s, 32, 4, -30);
|
||||
VDUP(vector2, q, int, s, 64, 2, 24);
|
||||
VDUP(vector2, q, uint, u, 8, 16, 12);
|
||||
VDUP(vector2, q, uint, u, 16, 8, 3);
|
||||
VDUP(vector2, q, uint, u, 32, 4, 55);
|
||||
VDUP(vector2, q, uint, u, 64, 2, 3);
|
||||
VDUP(vector2, q, poly, p, 8, 16, 12);
|
||||
VDUP(vector2, q, poly, p, 16, 8, 3);
|
||||
|
||||
/* Use maximum allowed shift amount. */
|
||||
TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 8);
|
||||
TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 16);
|
||||
TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 32);
|
||||
TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 64);
|
||||
TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 8);
|
||||
TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 16);
|
||||
TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 32);
|
||||
TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 64);
|
||||
TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 8);
|
||||
TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 16);
|
||||
TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 8);
|
||||
TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 16);
|
||||
TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 32);
|
||||
TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 64);
|
||||
TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 8);
|
||||
TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 16);
|
||||
TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 32);
|
||||
TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 64);
|
||||
TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 8);
|
||||
TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 16);
|
||||
|
||||
CHECK_RESULTS_NAMED (TEST_MSG, expected_max_shift, "(max shift amount)");
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue